LoadStoreMultiple optimization has been moved to the standalone pass so
it can be expanded. Potentially, its position in a pipeline could be
changed.

Additional support is added to recognize more sequences. Before,
a sequence like this wasn't accepted:

lw a1, 4(a0)
lw a3, 12(a0)
lw a2, 8(a0)

Now, when we're sorting instructions by the reg:offset pair internally,
the above is accepted.

Beside regular instruction sequence, we're also looking for an
instruction sequence that's "missing" one(or more) instruction to be
complete and interchangeable with lwm/swm instruction. The sequence is
optimizable if the Rt register in missing instruction is available.

We're handling the situation where the instruction sequence is regular,
except for one instruction having a "wrong" Rt register number. A
sequence like that is optimizable if the register with the expected
register number is available. In that case, we're emitting one
additional move instruction after lwm/swm.

This reverts commit 5ea10a5.