feat(difftest): add 'pc' and 'robidx' for store event (#3862)

src/main/scala/xiangshan/XSCore.scala

@@ -172,6 +172,8 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   backend.io.perf.retiredInstr := DontCare
   backend.io.perf.ctrlInfo := DontCare
 
+  backend.io.mem.storeDebugInfo <> memBlock.io.mem_to_ooo.storeDebugInfo
+
   // top -> memBlock
   memBlock.io.fromTopToBackend.clintTime := io.clintTime
   memBlock.io.fromTopToBackend.msiInfo := io.msiInfo

src/main/scala/xiangshan/backend/Backend.scala

@@ -729,6 +729,7 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
   // mem io
   io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO
   io.mem.robLsqIO <> ctrlBlock.io.robio.lsq
+  io.mem.storeDebugInfo <> ctrlBlock.io.robio.storeDebugInfo
 
   io.frontendSfence := fenceio.sfence
   io.frontendTlbCsr := csrio.tlb
@@ -912,6 +913,12 @@ class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBund
       writebackVldu ++
       writebackStd
   }
+
+  // store event difftest information
+  val storeDebugInfo = Vec(EnsbufferWidth, new Bundle {
+    val robidx = Input(new RobPtr)
+    val pc     = Output(UInt(VAddrBits.W))
+  })
 }
 
 class TopToBackendBundle(implicit p: Parameters) extends XSBundle {

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -622,6 +622,8 @@ class CtrlBlockImp(
 
   io.robio.robDeqPtr := rob.io.robDeqPtr
 
+  io.robio.storeDebugInfo <> rob.io.storeDebugInfo
+
   // rob to backend
   io.robio.commitVType := rob.io.toDecode.commitVType
   // exu block to decode
@@ -730,6 +732,12 @@ class CtrlBlockIO()(implicit p: Parameters, params: BackendParams) extends XSBun
       val hasVsetvl = Output(Bool())
     }
     val criticalError = Input(Bool())
+
+    // store event difftest information
+    val storeDebugInfo = Vec(EnsbufferWidth, new Bundle {
+      val robidx = Input(new RobPtr)
+      val pc     = Output(UInt(VAddrBits.W))
+    })
   }
 
   val toDecode = new Bundle {

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -147,6 +147,12 @@ class mem_to_ooo(implicit p: Parameters) extends MemBlockBundle {
     val lqCanAccept = Output(Bool())
     val sqCanAccept = Output(Bool())
   }
+
+  val storeDebugInfo = Vec(EnsbufferWidth, new Bundle {
+    val robidx = Output(new RobPtr)
+    val pc     = Input(UInt(VAddrBits.W))
+  })
+
   val writebackLda = Vec(LduCnt, DecoupledIO(new MemExuOutput))
   val writebackSta = Vec(StaCnt, DecoupledIO(new MemExuOutput))
   val writebackStd = Vec(StdCnt, DecoupledIO(new MemExuOutput))
@@ -1888,6 +1894,15 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
   }
   io.resetInFrontendBypass.toL2Top := io.resetInFrontendBypass.fromFrontend
 
+  io.mem_to_ooo.storeDebugInfo := DontCare
+  // store event difftest information
+  if (env.EnableDifftest) {
+    (0 until EnsbufferWidth).foreach{i =>
+        io.mem_to_ooo.storeDebugInfo(i).robidx := sbuffer.io.vecDifftestInfo(i).bits.robIdx
+        sbuffer.io.vecDifftestInfo(i).bits.pc := io.mem_to_ooo.storeDebugInfo(i).pc
+    }
+  }
+
   // top-down info
   dcache.io.debugTopDown.robHeadVaddr := io.debugTopDown.robHeadVaddr
   dtlbRepeater.io.debugTopDown.robHeadVaddr := io.debugTopDown.robHeadVaddr

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -111,6 +111,12 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
       val robHeadLqIdx = Valid(new LqPtr)
     }
     val debugRolling = new RobDebugRollingIO
+
+    // store event difftest information
+    val storeDebugInfo = Vec(EnsbufferWidth, new Bundle {
+      val robidx = Input(new RobPtr)
+      val pc     = Output(UInt(VAddrBits.W))
+    })
   })
 
   val exuWBs: Seq[ValidIO[ExuOutput]] = io.exuWriteback.filter(!_.bits.params.hasStdFu).toSeq
@@ -1491,6 +1497,14 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
     diffCriticalErrorEvent.criticalError := io.criticalError
   }
 
+  //store evetn difftest information
+  io.storeDebugInfo := DontCare
+  if (env.EnableDifftest) {
+    io.storeDebugInfo.map{port =>
+      port.pc := debug_microOp(port.robidx.value).pc
+    }
+  }
+
   val commitLoadVec = VecInit(commitLoadValid)
   val commitBranchVec = VecInit(commitBranchValid)
   val commitStoreVec = VecInit(io.commits.commitValid.zip(commitIsStore).map { case (v, t) => v && t })

src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala

@@ -946,6 +946,8 @@ class Sbuffer(implicit p: Parameters)
         difftestCommon.addr   := waddr
         difftestCommon.data   := wdata
         difftestCommon.mask   := wmask
+        difftestCommon.robidx := io.vecDifftestInfo(i).bits.robIdx.value
+        difftestCommon.pc     := io.vecDifftestInfo(i).bits.pc
 
       } .elsewhen (!isWline) {
         val storeCommit       = io.in(i).fire
@@ -961,7 +963,8 @@ class Sbuffer(implicit p: Parameters)
         difftestCommon.addr   := waddr
         difftestCommon.data   := wdata
         difftestCommon.mask   := wmask
-
+        difftestCommon.robidx := io.vecDifftestInfo(i).bits.robIdx.value
+        difftestCommon.pc     := io.vecDifftestInfo(i).bits.pc
       }
 
       for (index <- 0 until WlineMaxNumber) {
@@ -977,7 +980,9 @@ class Sbuffer(implicit p: Parameters)
           difftest.addr   := blockAddr + (index.U << wordOffBits)
           difftest.data   := io.in(i).bits.data
           difftest.mask   := ((1 << wordBytes) - 1).U
-
+          difftest.robidx := io.vecDifftestInfo(i).bits.robIdx.value
+          difftest.pc     := io.vecDifftestInfo(i).bits.pc
+
           assert(!storeCommit || (io.in(i).bits.data === 0.U), "wline only supports whole zero write now")
         }
       }
@@ -1009,7 +1014,8 @@ class Sbuffer(implicit p: Parameters)
           difftest.addr   := waddr
           difftest.data   := wdata
           difftest.mask   := wmask
-
+          difftest.robidx := io.vecDifftestInfo(i).bits.robIdx.value
+          difftest.pc     := io.vecDifftestInfo(i).bits.pc
         }
       }
     }