area(StoreUnit): source from StoreMisalignBuffer don't need store uop…

….imm(32bits), because can use vaddr directly
OpenXiangShan · Oct 29, 2024 · a592590 · a592590
1 parent f1b784f
commit a592590
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala b/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
@@ -126,7 +126,7 @@ class StoreUnit(implicit p: Parameters) extends XSModule
   val s0_vecBaseVaddr = s0_vecstin.basevaddr
 
   // generate addr
-  val s0_saddr = s0_stin.src(0) + SignExt(s0_uop.imm(11,0), VAddrBits)
+  val s0_saddr = s0_stin.src(0) + SignExt(s0_stin.uop.imm(11,0), VAddrBits)
   val s0_fullva = Wire(UInt(XLEN.W))
   val s0_vaddr = Mux(
     s0_use_flow_ma,
@@ -143,7 +143,7 @@ class StoreUnit(implicit p: Parameters) extends XSModule
   )
   s0_fullva := Mux(
     s0_use_flow_rs,
-    s0_stin.src(0) + SignExt(s0_uop.imm(11,0), XLEN),
+    s0_stin.src(0) + SignExt(s0_stin.uop.imm(11,0), XLEN),
     Mux(
       s0_use_flow_vec,
       s0_vecstin.vaddr,