busytable: support eliminate old vd when read vl's state

src/main/scala/xiangshan/Parameters.scala

@@ -213,6 +213,8 @@ case class XSCoreParameters
   ),
   IntRegCacheSize: Int = 16,
   MemRegCacheSize: Int = 12,
+  intSchdVlWbPort: Int = 0,
+  vfSchdVlWbPort: Int = 1,
   prefetcher: Option[PrefetcherParams] = Some(SMSParams()),
   IfuRedirectNum: Int = 1,
   LoadPipelineWidth: Int = 3,
@@ -386,7 +388,7 @@ case class XSCoreParameters
       ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
       IssueBlockParams(Seq(
         ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2),
-        ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))),
+        ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))),
       ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
       IssueBlockParams(Seq(
         ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2),
@@ -434,7 +436,7 @@ case class XSCoreParameters
     SchdBlockParams(Seq(
       IssueBlockParams(Seq(
         ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))),
-        ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))),
+        ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))),
       ), numEntries = 16, numEnq = 2, numComp = 14),
       IssueBlockParams(Seq(
         ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))),

src/main/scala/xiangshan/backend/Backend.scala

@@ -12,6 +12,13 @@
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 *
 * See the Mulan PSL v2 for more details.
+*
+*
+* Acknowledgement
+*
+* This implementation is inspired by several key papers:
+* [1] R. M. Tomasulo. "[An efficient algorithm for exploiting multiple arithmetic units.]
+* (https://doi.org/10.1147/rd.111.0025)" IBM Journal of research and Development 11.1 (1967): 25-33.
 ***************************************************************************************/
 
 package xiangshan.backend

src/main/scala/xiangshan/backend/Bundles.scala

@@ -442,7 +442,7 @@ object Bundles {
     val isOpMask  = Bool() // vmand, vmnand
     val isMove    = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i
 
-    val isDependOldvd = Bool() // some instruction's computation depends on oldvd
+    val isDependOldVd = Bool() // some instruction's computation depends on oldvd
     val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum
 
     val isVleff = Bool() // vleff

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -1043,7 +1043,7 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
     decodedInst.vpu.isNarrow := isNarrow
     decodedInst.vpu.isDstMask := isDstMask
     decodedInst.vpu.isOpMask := isOpMask
-    decodedInst.vpu.isDependOldvd := isVppu || isVecOPF || isVStore || (isDstMask && !isOpMask) || isNarrow || isVlx || isVma
+    decodedInst.vpu.isDependOldVd := isVppu || isVecOPF || isVStore || (isDstMask && !isOpMask) || isNarrow || isVlx || isVma
     decodedInst.vpu.isWritePartVd := isWritePartVd || isVlm || isVle && emulIsFrac
     decodedInst.vpu.vstart := io.enq.vstart
     decodedInst.vpu.isVleff := decodedInst.fuOpType === VlduType.vleff && inst.NF === 0.U

src/main/scala/xiangshan/backend/decode/FPDecoder.scala

@@ -141,7 +141,7 @@ class FPToVecDecoder(implicit p: Parameters) extends XSModule {
   io.vpuCtrl.isNarrow  := false.B
   io.vpuCtrl.isDstMask := false.B
   io.vpuCtrl.isOpMask  := false.B
-  io.vpuCtrl.isDependOldvd := false.B
+  io.vpuCtrl.isDependOldVd := false.B
   io.vpuCtrl.isWritePartVd := false.B
 }
 

src/main/scala/xiangshan/backend/fu/Multiplier.scala

@@ -12,6 +12,15 @@
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 *
 * See the Mulan PSL v2 for more details.
+*
+*
+* Acknowledgement
+*
+* This implementation is inspired by several key papers:
+* [1] Andrew D. Booth. "[A signed binary multiplication technique.](https://doi.org/10.1093/qjmam/4.2.236)" The
+* Quarterly Journal of Mechanics and Applied Mathematics 4.2 (1951): 236-240.
+* [2] C. S. Wallace. "[A suggestion for a fast multiplier.](https://doi.org/10.1109/PGEC.1964.263830)" IEEE
+* Transactions on electronic Computers 1 (1964): 14-17.
 ***************************************************************************************/
 
 package xiangshan.backend.fu

src/main/scala/xiangshan/backend/fu/SRT16Divider.scala

@@ -13,6 +13,13 @@
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 *
 * See the Mulan PSL v2 for more details.
+*
+*
+* Acknowledgement
+*
+* This implementation is inspired by several key papers:
+* [1] Elisardo Antelo, Tomas Lang, Paolo Montuschi, and Alberto Nannarelli. "[Digit-recurrence dividers with reduced
+* logical depth.](https://doi.org/10.1109/TC.2005.115)" IEEE Transactions on Computers 54.7 (2005): 837-851.
 ***************************************************************************************/
 
 // This file contains components originally written by Yifei He, see

src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala

@@ -8,7 +8,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import utility._
 import xiangshan._
 import xiangshan.backend.fu.{FuConfig, FuType}
-import xiangshan.backend.rename.BusyTableReadIO
+import xiangshan.backend.rename.{BusyTableReadIO,VlBusyTableReadIO}
 import xiangshan.mem._
 import xiangshan.backend.Bundles.{DynInst, ExuOH}
 import xiangshan.backend.datapath.DataSource
@@ -112,6 +112,7 @@ abstract class Dispatch2IqImp(override val wrapper: Dispatch2Iq)(implicit p: Par
     val readVfState = if (numVfStateRead > 0) Some(Vec(numVfStateRead, Flipped(new BusyTableReadIO))) else None
     val readV0State = if (numV0StateRead > 0) Some(Vec(numV0StateRead, Flipped(new BusyTableReadIO))) else None
     val readVlState = if (numVlStateRead > 0) Some(Vec(numVlStateRead, Flipped(new BusyTableReadIO))) else None
+    val readVlInfo  = if (numVlStateRead > 0) Some(Vec(numVlStateRead, Flipped(new VlBusyTableReadIO))) else None
     val readRCTagTableState = Option.when(numRCTagTableStateRead > 0)(Vec(numRCTagTableStateRead, Flipped(new RCTagTableReadPort(RegCacheIdxWidth, params.pregIdxWidth))))
     val out = MixedVec(params.issueBlockParams.filter(iq => iq.StdCnt == 0).map(x => Vec(x.numEnq, DecoupledIO(new DynInst))))
     val enqLsqIO = if (wrapper.isMem) Some(Flipped(new LsqEnqIO)) else None
@@ -139,6 +140,8 @@ abstract class Dispatch2IqImp(override val wrapper: Dispatch2Iq)(implicit p: Par
   private val vfSrcStateVec  = Option.when(io.readVfState.isDefined )(Wire(Vec(numVfStateRead, SrcState()))) 
   private val v0SrcStateVec  = Option.when(io.readV0State.isDefined )(Wire(Vec(numV0StateRead, SrcState())))
   private val vlSrcStateVec  = Option.when(io.readVlState.isDefined )(Wire(Vec(numVlStateRead, SrcState())))
+  private val vlSrcIsZeroVec  = Option.when(io.readVlInfo.isDefined )(Wire(Vec(numVlStateRead, Bool())))
+  private val vlSrcIsVlMaxVec  = Option.when(io.readVlInfo.isDefined )(Wire(Vec(numVlStateRead, Bool())))
   private val intAllSrcStateVec = Option.when(io.readIntState.isDefined)(Wire(Vec(numIn * numRegSrc, SrcState())))
   private val fpAllSrcStateVec  = Option.when(io.readFpState.isDefined )(Wire(Vec(numIn * numRegSrc, SrcState())))
   private val vecAllSrcStateVec = Option.when(io.readVfState.isDefined )(Wire(Vec(numIn * numRegSrc, SrcState())))
@@ -204,6 +207,8 @@ abstract class Dispatch2IqImp(override val wrapper: Dispatch2Iq)(implicit p: Par
 
     io.readVlState.get.map(_.req).zip(vlReqPsrcVec).foreach(x => x._1 := x._2)
     io.readVlState.get.map(_.resp).zip(vlSrcStateVec.get).foreach(x => x._2 := x._1)
+    io.readVlInfo.get.map(_.is_zero).zip(vlSrcIsZeroVec.get).foreach(x => x._2 := x._1)
+    io.readVlInfo.get.map(_.is_vlmax).zip(vlSrcIsVlMaxVec.get).foreach(x => x._2 := x._1)
     io.readVlState.get.map(_.loadDependency).zip(vlSrcLoadDependency.get).foreach(x => x._2 := x._1)
 
     for (i <- 0 until numIn) {
@@ -215,6 +220,31 @@ abstract class Dispatch2IqImp(override val wrapper: Dispatch2Iq)(implicit p: Par
       vecAllSrcStateVec.get(i * numRegSrc + numRegSrc - 1)       := vlSrcStateVec.get(i);
       vecAllSrcLoadDependency.get(i * numRegSrc + numRegSrc - 2) := v0SrcLoadDependency.get(i);
       vecAllSrcLoadDependency.get(i * numRegSrc + numRegSrc - 1) := vlSrcLoadDependency.get(i);
+
+      // same as eliminate the old vd dependency in issue queue when wake up by wakeup
+      val isDependOldVd = io.in(i).bits.vpu.isDependOldVd
+      val isWritePartVd = io.in(i).bits.vpu.isWritePartVd
+      val vta = io.in(i).bits.vpu.vta
+      val vma = io.in(i).bits.vpu.vma
+      val vm = io.in(i).bits.vpu.vm
+      val vlIsVlmax = vlSrcIsVlMaxVec.get(i)
+      val vlIsZero = vlSrcIsZeroVec.get(i)
+      val vlIsNonZero = !vlSrcIsZeroVec.get(i)
+      val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd
+      val ignoreWhole = (vm =/= 0.U || vma) && vta
+      val isFof = VlduType.isFof(io.in(i).bits.fuOpType)
+      for (j <- 0 until numRegSrcVf) {
+        val ignoreOldVd = Wire(Bool())
+        if (j == numRegSrcVf - 1) {
+          // check whether can ignore the old vd dependency
+          ignoreOldVd := SrcState.isReady(vlSrcStateVec.get(i)) && !isFof && vlIsNonZero && !isDependOldVd && (ignoreTail || ignoreWhole)
+        } else {
+          // check whether can ignore the src
+          ignoreOldVd := false.B
+        }
+        uopsIn(i).bits.srcType(j) := Mux(ignoreOldVd, SrcType.no, io.in(i).bits.srcType(j))
+        vecAllSrcStateVec.get(i * numRegSrc + j) := Mux(ignoreOldVd, SrcState.rdy, vfSrcStateVec.get(i * numRegSrcVf + j))
+      }
     }
   }
   if (io.readRCTagTableState.isDefined) {

src/main/scala/xiangshan/backend/issue/EntryBundles.scala

@@ -208,10 +208,12 @@ object EntryBundles extends HasCircularQueuePtrHelper {
       })
       var numVecWb = params.backendParam.getVfWBExeGroup.size
       var numV0Wb = params.backendParam.getV0WBExeGroup.size
+      var intSchdVlWbPort = p(XSCoreParamsKey).intSchdVlWbPort
+      var vfSchdVlWbPort = p(XSCoreParamsKey).vfSchdVlWbPort
       // int wb is first bit of vlwb, which is after vfwb and v0wb
-      common.vlWakeupByIntWb  := wakeUpFromVl(numVecWb + numV0Wb)
+      common.vlWakeupByIntWb  := wakeUpFromVl(numVecWb + numV0Wb + intSchdVlWbPort)
       // vf wb is second bit of wb
-      common.vlWakeupByVfWb   := wakeUpFromVl(numVecWb + numV0Wb + 1)
+      common.vlWakeupByVfWb   := wakeUpFromVl(numVecWb + numV0Wb + vfSchdVlWbPort)
     } else {
       common.vlWakeupByIntWb  := false.B
       common.vlWakeupByVfWb   := false.B
@@ -298,7 +300,7 @@ object EntryBundles extends HasCircularQueuePtrHelper {
       val ignoreOldVd = Wire(Bool())
       val vlWakeUpByIntWb = common.vlWakeupByIntWb
       val vlWakeUpByVfWb = common.vlWakeupByVfWb
-      val isDependOldvd = entryReg.payload.vpu.isDependOldvd
+      val isDependOldVd = entryReg.payload.vpu.isDependOldVd
       val isWritePartVd = entryReg.payload.vpu.isWritePartVd
       val vta = entryReg.payload.vpu.vta
       val vma = entryReg.payload.vpu.vma
@@ -319,7 +321,7 @@ object EntryBundles extends HasCircularQueuePtrHelper {
           * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value
           * 3. when vl = vlmax, we can set srctype to imm when vta is not set
           */
-        ignoreOldVd := !VlduType.isFof(entryReg.payload.fuOpType) && srcIsVec && vlIsNonZero && !isDependOldvd && (ignoreTail || ignoreWhole)
+        ignoreOldVd := !VlduType.isFof(entryReg.payload.fuOpType) && srcIsVec && vlIsNonZero && !isDependOldVd && (ignoreTail || ignoreWhole)
       } else {
         ignoreOldVd := false.B
       }

src/main/scala/xiangshan/backend/issue/Scheduler.scala

@@ -12,7 +12,7 @@ import xiangshan.backend.datapath.DataConfig._
 import xiangshan.backend.datapath.WbConfig._
 import xiangshan.backend.fu.FuType
 import xiangshan.backend.regfile.RfWritePortWithConfig
-import xiangshan.backend.rename.BusyTable
+import xiangshan.backend.rename.{BusyTable, VlBusyTable}
 import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr}
 import xiangshan.backend.datapath.WbConfig.V0WB
 import xiangshan.backend.regfile.VlPregParams
@@ -185,7 +185,7 @@ abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockPa
     case _ => None
   }
   val vlBusyTable = schdType match {
-    case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVlStateRead, wrapper.numVlStateWrite, VlPhyRegs, VlWB())))
+    case VfScheduler() | MemScheduler() => Some(Module(new VlBusyTable(dispatch2Iq.numVlStateRead, wrapper.numVlStateWrite, VlPhyRegs, VlWB())))
     case _ => None
   }
 
@@ -203,6 +203,7 @@ abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockPa
     dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read)
     dp2iq.readV0State.foreach(_ <> v0BusyTable.get.io.read)
     dp2iq.readVlState.foreach(_ <> vlBusyTable.get.io.read)
+    dp2iq.readVlInfo.foreach(_ <> vlBusyTable.get.io_vl_read.vlReadInfo)
     dp2iq.readRCTagTableState.foreach(_ <> rcTagTable.get.io.readPorts)
   }
 
@@ -283,6 +284,8 @@ abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockPa
       bt.io.wakeUp := io.fromSchedulers.wakeupVec
       bt.io.og0Cancel := io.fromDataPath.og0Cancel
       bt.io.ldCancel := io.ldCancel
+
+      bt.io_vl_Wb.vlWriteBackInfo := io.vlWriteBackInfo
     case None =>
   }
 

src/main/scala/xiangshan/backend/rename/BusyTable.scala

@@ -33,6 +33,11 @@ class BusyTableReadIO(implicit p: Parameters) extends XSBundle {
   val loadDependency = Vec(LoadPipelineWidth, Output(UInt(LoadDependencyWidth.W)))
 }
 
+class VlBusyTableReadIO(implicit p: Parameters) extends XSBundle {
+  val is_zero = Output(Bool())
+  val is_vlmax = Output(Bool())
+}
+
 class BusyTable(numReadPorts: Int, numWritePorts: Int, numPhyPregs: Int, pregWB: PregWB)(implicit p: Parameters, params: SchdBlockParams) extends XSModule with HasPerfEvents {
   val io = IO(new Bundle() {
     // set preg state to busy
@@ -179,3 +184,68 @@ class BusyTable(numReadPorts: Int, numWritePorts: Int, numPhyPregs: Int, pregWB:
   )
   generatePerfEvent()
 }
+
+class VlBusyTable(numReadPorts: Int, numWritePorts: Int, numPhyPregs: Int, pregWB: PregWB)(implicit p: Parameters, params: SchdBlockParams) extends BusyTable(numReadPorts, numWritePorts, numPhyPregs, pregWB) {
+
+  val io_vl_Wb = IO(new Bundle() {
+    val vlWriteBackInfo = new Bundle {
+      val vlFromIntIsZero  = Input(Bool())
+      val vlFromIntIsVlmax = Input(Bool())
+      val vlFromVfIsZero   = Input(Bool())
+      val vlFromVfIsVlmax  = Input(Bool())
+    }
+  })
+  val io_vl_read = IO(new Bundle() {
+    val vlReadInfo = Vec(numReadPorts, new VlBusyTableReadIO)
+  })
+
+  var intSchdVlWbPort = p(XSCoreParamsKey).intSchdVlWbPort
+  var vfSchdVlWbPort = p(XSCoreParamsKey).vfSchdVlWbPort
+
+  val zeroTableUpdate = Wire(Vec(numPhyPregs, Bool()))
+  val vlmaxTableUpdate = Wire(Vec(numPhyPregs, Bool()))
+
+  val wb0Mask = Mux(io.wbPregs(intSchdVlWbPort).valid, UIntToOH(io.wbPregs(intSchdVlWbPort).bits), 0.U)
+  val wb1Mask = Mux(io.wbPregs(vfSchdVlWbPort).valid, UIntToOH(io.wbPregs(vfSchdVlWbPort).bits), 0.U)
+
+  val zeroTable = VecInit((0 until numPhyPregs).zip(zeroTableUpdate).map{ case (idx, update) =>
+    RegEnable(update, 0.U(1.W), allocMask(idx) || ldCancelMask(idx) || wb0Mask(idx) || wb1Mask(idx))
+  }).asUInt
+  val vlmaxTable = VecInit((0 until numPhyPregs).zip(vlmaxTableUpdate).map{ case (idx, update) =>
+    RegEnable(update, 0.U(1.W), allocMask(idx) || ldCancelMask(idx) || wb0Mask(idx) || wb1Mask(idx))
+  }).asUInt
+
+
+  zeroTableUpdate.zipWithIndex.foreach{ case (update, idx) =>
+    when(wb0Mask(idx)) {
+      // int schd vl write back, check whether the vl is zero
+      update := !io_vl_Wb.vlWriteBackInfo.vlFromIntIsZero
+    }.elsewhen(wb1Mask(idx)) {
+      // vf schd vl write back, check whether the vl is zero
+      update := !io_vl_Wb.vlWriteBackInfo.vlFromVfIsZero
+    }.elsewhen(allocMask(idx) || ldCancelMask(idx)) {
+      update := true.B
+    }.otherwise {
+      update := zeroTable(idx)
+    }
+  }
+
+  vlmaxTableUpdate.zipWithIndex.foreach{ case (update, idx) =>
+    when(wb1Mask(idx)) {
+      // int schd vl write back, check whether the vl is vlmax
+      update := !io_vl_Wb.vlWriteBackInfo.vlFromIntIsVlmax
+    }.elsewhen(wb1Mask(idx)) {
+      // vf schd vl write back, check whether the vl is vlmax
+      update := !io_vl_Wb.vlWriteBackInfo.vlFromVfIsVlmax
+    }.elsewhen(allocMask(idx) || ldCancelMask(idx)) {
+      update := true.B
+    }.otherwise {
+      update := vlmaxTable(idx)
+    }
+  }
+
+  io_vl_read.vlReadInfo.zip(io.read).foreach{ case (vlRes, res) =>
+    vlRes.is_zero := !zeroTable(res.req)
+    vlRes.is_vlmax := !vlmaxTable(res.req)
+  }
+}

src/main/scala/xiangshan/backend/rename/CompressUnit.scala

@@ -1,3 +1,28 @@
+/***************************************************************************************
+* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
+* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
+* Copyright (c) 2020-2021 Peng Cheng Laboratory
+*
+* XiangShan is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*          http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+*
+* See the Mulan PSL v2 for more details.
+*
+*
+* Acknowledgement
+*
+* This implementation is inspired by several key papers:
+* [1] Fernando Latorre, Grigorios Magklis, Jose González, Pedro Chaparro, and Antonio González. "[Crob: implementing a
+* large instruction window through compression.](https://doi.org/10.1007/978-3-642-19448-1_7)" Transactions on high-
+* performance embedded architectures and compilers III. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. 115-134.
+***************************************************************************************/
+
 package xiangshan.backend.rename
 
 import org.chipsalliance.cde.config.Parameters

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -12,6 +12,13 @@
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 *
 * See the Mulan PSL v2 for more details.
+*
+*
+* Acknowledgement
+*
+* This implementation is inspired by several key papers:
+* [1] James E. Smith, and Andrew R. Pleszkun. "[Implementation of precise interrupts in pipelined processors.]
+* (https://doi.org/10.1145/327070.327125)" ACM SIGARCH Computer Architecture News 13.3 (1985): 36-44.
 ***************************************************************************************/
 
 package xiangshan.backend.rob

src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala

@@ -13,6 +13,14 @@
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 *
 * See the Mulan PSL v2 for more details.
+*
+*
+* Acknowledgement
+*
+* This implementation is inspired by several key papers:
+* [1] Gurindar S. Sohi, and Manoj Franklin "[High-bandwidth data memory systems for superscalar processors.]
+* (https://doi.org/10.1145/106973.106980)" Proceedings of the fourth international conference on Architectural support
+* for programming languages and operating systems. 1991.
 ***************************************************************************************/
 
 package xiangshan.cache