Merge branch 'OpenXiangShan:master' into master

README.md

@@ -10,7 +10,7 @@ Copyright 2020-2022 by Peng Cheng Laboratory.
 
 ## Docs and slides
 
-[XiangShan-doc](https://github.com/OpenXiangShan/XiangShan-doc) is our official documentation repository. It contains design spec., technical slides, tutorial and more.
+[XiangShan-doc](https://github.com/OpenXiangShan/XiangShan-doc) is our official documentation repository. It contains design spec., technical slides, tutorials and more.
 
 * Micro-architecture documentation of XiangShan has been published. Please check out https://xiangshan-doc.readthedocs.io
 
@@ -38,13 +38,13 @@ Zhihu/知乎：[香山开源处理器](https://www.zhihu.com/people/openxiangsha
 
 Weibo/微博：[香山开源处理器](https://weibo.com/u/7706264932)
 
-You can contact us through [our mail list](mailto:[email protected]). All mails from this list will be archived to [here](https://www.mail-archive.com/[email protected]/).
+You can contact us through [our mailing list](mailto:[email protected]). All mails from this list will be archived [here](https://www.mail-archive.com/[email protected]/).
 
 ## Architecture
 
-The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) [on the yanqihu branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June 2020.
+The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) and is [on the yanqihu branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June 2020.
 
-The second stable micro-architecture of XiangShan is called Nanhu (南湖) [on the nanhu branch](https://github.com/OpenXiangShan/XiangShan/tree/nanhu).
+The second stable micro-architecture of XiangShan is called Nanhu (南湖) and is [on the nanhu branch](https://github.com/OpenXiangShan/XiangShan/tree/nanhu).
 
 The current version of XiangShan, also known as Kunminghu (昆明湖), is still under development on the master branch.
 

src/main/scala/top/Configs.scala

@@ -408,7 +408,7 @@ class FuzzConfig(dummy: Int = 0) extends Config(
 class DefaultConfig(n: Int = 1) extends Config(
   new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16)
     ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4)
-    ++ new WithNKBL1D(64, ways = 8)
+    ++ new WithNKBL1D(64, ways = 4)
     ++ new BaseConfig(n)
 )
 
@@ -422,7 +422,7 @@ class KunminghuV2Config(n: Int = 1) extends Config(
       case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3
     })
     ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false)
-    ++ new WithNKBL1D(64, ways = 8)
+    ++ new WithNKBL1D(64, ways = 4)
     ++ new DefaultConfig(n)
 )
 
@@ -435,7 +435,7 @@ class XSNoCTopConfig(n: Int = 1) extends Config(
 class FpgaDefaultConfig(n: Int = 1) extends Config(
   (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6)
     ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4)
-    ++ new WithNKBL1D(64, ways = 8)
+    ++ new WithNKBL1D(64, ways = 4)
     ++ new BaseConfig(n)).alter((site, here, up) => {
     case DebugOptionsKey => up(DebugOptionsKey).copy(
       AlwaysBasicDiff = false,

src/main/scala/xiangshan/Parameters.scala

@@ -213,6 +213,8 @@ case class XSCoreParameters
   ),
   IntRegCacheSize: Int = 16,
   MemRegCacheSize: Int = 12,
+  intSchdVlWbPort: Int = 0,
+  vfSchdVlWbPort: Int = 1,
   prefetcher: Option[PrefetcherParams] = Some(SMSParams()),
   IfuRedirectNum: Int = 1,
   LoadPipelineWidth: Int = 3,
@@ -386,7 +388,7 @@ case class XSCoreParameters
       ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
       IssueBlockParams(Seq(
         ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2),
-        ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))),
+        ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))),
       ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
       IssueBlockParams(Seq(
         ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2),
@@ -434,7 +436,7 @@ case class XSCoreParameters
     SchdBlockParams(Seq(
       IssueBlockParams(Seq(
         ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))),
-        ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))),
+        ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))),
       ), numEntries = 16, numEnq = 2, numComp = 14),
       IssueBlockParams(Seq(
         ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))),

src/main/scala/xiangshan/backend/Bundles.scala

@@ -442,7 +442,7 @@ object Bundles {
     val isOpMask  = Bool() // vmand, vmnand
     val isMove    = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i
 
-    val isDependOldvd = Bool() // some instruction's computation depends on oldvd
+    val isDependOldVd = Bool() // some instruction's computation depends on oldvd
     val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum
 
     val isVleff = Bool() // vleff

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -62,6 +62,10 @@ trait HasMemBlockParameters extends HasXSParameter {
   val MemExuCnt = LduCnt + HyuCnt + StaCnt + StdCnt
   val MemAddrExtCnt = LdExuCnt + StaCnt
   val MemVExuCnt = VlduCnt + VstuCnt
+
+  val AtomicWBPort   = 0
+  val MisalignWBPort = 1
+  val UncacheWBPort  = 2
 }
 
 abstract class MemBlockBundle(implicit val p: Parameters) extends Bundle with HasMemBlockParameters
@@ -433,24 +437,32 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
   hybridUnits.zipWithIndex.map(x => x._1.suggestName("HybridUnit_"+x._2))
   val atomicsUnit = Module(new AtomicsUnit)
 
-  val ldaWritebackOverride  = Mux(
-    loadMisalignBuffer.io.writeBack.valid,
-    loadMisalignBuffer.io.writeBack.bits,
-    Mux(
-      atomicsUnit.io.out.valid,
-      atomicsUnit.io.out.bits,
-      loadUnits.head.io.ldout.bits
-    ))
-  val ldaOut = Wire(Decoupled(new MemExuOutput))
+
+  val ldaExeWbReqs = Wire(Vec(LduCnt, Decoupled(new MemExuOutput)))
+  // atomicsUnit will overwrite the source from ldu if it is about to writeback
+  val atomicWritebackOverride = Mux(
+    atomicsUnit.io.out.valid,
+    atomicsUnit.io.out.bits,
+    loadUnits(AtomicWBPort).io.ldout.bits
+  )
+  ldaExeWbReqs(AtomicWBPort).valid := atomicsUnit.io.out.valid || loadUnits(AtomicWBPort).io.ldout.valid
+  ldaExeWbReqs(AtomicWBPort).bits  := atomicWritebackOverride
+  atomicsUnit.io.out.ready := ldaExeWbReqs(AtomicWBPort).ready
+  loadUnits(AtomicWBPort).io.ldout.ready := ldaExeWbReqs(AtomicWBPort).ready
+
   // misalignBuffer will overwrite the source from ldu if it is about to writeback
-  ldaOut.valid := atomicsUnit.io.out.valid || loadUnits.head.io.ldout.valid || loadMisalignBuffer.io.writeBack.valid
-  ldaOut.bits  := ldaWritebackOverride
-  ldaOut.bits.isFromLoadUnit := !(atomicsUnit.io.out.valid || loadMisalignBuffer.io.writeBack.valid)
-  atomicsUnit.io.out.ready := ldaOut.ready
-  loadUnits.head.io.ldout.ready := ldaOut.ready
-  loadMisalignBuffer.io.writeBack.ready := ldaOut.ready
-
-  val ldaExeWbReqs = ldaOut +: loadUnits.tail.map(_.io.ldout)
+  val misalignWritebackOverride = Mux(
+     loadMisalignBuffer.io.writeBack.valid,
+     loadMisalignBuffer.io.writeBack.bits,
+     loadUnits(MisalignWBPort).io.ldout.bits
+  )
+  ldaExeWbReqs(MisalignWBPort).valid := loadMisalignBuffer.io.writeBack.valid || loadUnits(MisalignWBPort).io.ldout.valid
+  ldaExeWbReqs(MisalignWBPort).bits  := misalignWritebackOverride
+  loadMisalignBuffer.io.writeBack.ready := ldaExeWbReqs(MisalignWBPort).ready
+  loadUnits(MisalignWBPort).io.ldout.ready := ldaExeWbReqs(MisalignWBPort).ready
+
+  // loadUnit will overwrite the source from uncache if it is about to writeback
+  ldaExeWbReqs(UncacheWBPort) <> loadUnits(UncacheWBPort).io.ldout
   io.mem_to_ooo.writebackLda <> ldaExeWbReqs
   io.mem_to_ooo.writebackSta <> storeUnits.map(_.io.stout)
   io.mem_to_ooo.writebackStd.zip(stdExeUnits).foreach {x =>
@@ -730,9 +742,9 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
   // After the segment instruction directive starts executing, no other instructions should be executed.
   val vSegmentFlag = RegInit(false.B)
 
-  when(vSegmentUnit.io.in.fire){
+  when(GatedValidRegNext(vSegmentUnit.io.in.fire)) {
     vSegmentFlag := true.B
-  }.elsewhen(vSegmentUnit.io.uopwriteback.valid){
+  }.elsewhen(GatedValidRegNext(vSegmentUnit.io.uopwriteback.valid)) {
     vSegmentFlag := false.B
   }
 
@@ -882,7 +894,13 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
 
     // passdown to lsq (load s2)
     lsq.io.ldu.ldin(i) <> loadUnits(i).io.lsq.ldin
-    lsq.io.ldout(i) <> loadUnits(i).io.lsq.uncache
+    if (i == UncacheWBPort) {
+      lsq.io.ldout(i) <> loadUnits(i).io.lsq.uncache
+    } else {
+      lsq.io.ldout(i).ready := true.B
+      loadUnits(i).io.lsq.uncache.valid := false.B
+      loadUnits(i).io.lsq.uncache.bits := DontCare
+    }
     lsq.io.ld_raw_data(i) <> loadUnits(i).io.lsq.ld_raw_data
     lsq.io.l2_hint.valid := l2_hint.valid
     lsq.io.l2_hint.bits.sourceId := l2_hint.bits.sourceId
@@ -1050,7 +1068,7 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
   }
 
   // misalignBuffer
-  loadMisalignBuffer.io.redirect                <> redirect  
+  loadMisalignBuffer.io.redirect                <> redirect
   loadMisalignBuffer.io.rob.lcommit             := io.ooo_to_mem.lsqio.lcommit
   loadMisalignBuffer.io.rob.scommit             := io.ooo_to_mem.lsqio.scommit
   loadMisalignBuffer.io.rob.pendingUncacheld    := io.ooo_to_mem.lsqio.pendingUncacheld

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -1043,7 +1043,7 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
     decodedInst.vpu.isNarrow := isNarrow
     decodedInst.vpu.isDstMask := isDstMask
     decodedInst.vpu.isOpMask := isOpMask
-    decodedInst.vpu.isDependOldvd := isVppu || isVecOPF || isVStore || (isDstMask && !isOpMask) || isNarrow || isVlx || isVma
+    decodedInst.vpu.isDependOldVd := isVppu || isVecOPF || isVStore || (isDstMask && !isOpMask) || isNarrow || isVlx || isVma
     decodedInst.vpu.isWritePartVd := isWritePartVd || isVlm || isVle && emulIsFrac
     decodedInst.vpu.vstart := io.enq.vstart
     decodedInst.vpu.isVleff := decodedInst.fuOpType === VlduType.vleff && inst.NF === 0.U

src/main/scala/xiangshan/backend/decode/FPDecoder.scala

@@ -141,7 +141,7 @@ class FPToVecDecoder(implicit p: Parameters) extends XSModule {
   io.vpuCtrl.isNarrow  := false.B
   io.vpuCtrl.isDstMask := false.B
   io.vpuCtrl.isOpMask  := false.B
-  io.vpuCtrl.isDependOldvd := false.B
+  io.vpuCtrl.isDependOldVd := false.B
   io.vpuCtrl.isWritePartVd := false.B
 }
 

src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala

@@ -8,7 +8,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import utility._
 import xiangshan._
 import xiangshan.backend.fu.{FuConfig, FuType}
-import xiangshan.backend.rename.BusyTableReadIO
+import xiangshan.backend.rename.{BusyTableReadIO,VlBusyTableReadIO}
 import xiangshan.mem._
 import xiangshan.backend.Bundles.{DynInst, ExuOH}
 import xiangshan.backend.datapath.DataSource
@@ -112,6 +112,7 @@ abstract class Dispatch2IqImp(override val wrapper: Dispatch2Iq)(implicit p: Par
     val readVfState = if (numVfStateRead > 0) Some(Vec(numVfStateRead, Flipped(new BusyTableReadIO))) else None
     val readV0State = if (numV0StateRead > 0) Some(Vec(numV0StateRead, Flipped(new BusyTableReadIO))) else None
     val readVlState = if (numVlStateRead > 0) Some(Vec(numVlStateRead, Flipped(new BusyTableReadIO))) else None
+    val readVlInfo  = if (numVlStateRead > 0) Some(Vec(numVlStateRead, Flipped(new VlBusyTableReadIO))) else None
     val readRCTagTableState = Option.when(numRCTagTableStateRead > 0)(Vec(numRCTagTableStateRead, Flipped(new RCTagTableReadPort(RegCacheIdxWidth, params.pregIdxWidth))))
     val out = MixedVec(params.issueBlockParams.filter(iq => iq.StdCnt == 0).map(x => Vec(x.numEnq, DecoupledIO(new DynInst))))
     val enqLsqIO = if (wrapper.isMem) Some(Flipped(new LsqEnqIO)) else None
@@ -139,6 +140,8 @@ abstract class Dispatch2IqImp(override val wrapper: Dispatch2Iq)(implicit p: Par
   private val vfSrcStateVec  = Option.when(io.readVfState.isDefined )(Wire(Vec(numVfStateRead, SrcState()))) 
   private val v0SrcStateVec  = Option.when(io.readV0State.isDefined )(Wire(Vec(numV0StateRead, SrcState())))
   private val vlSrcStateVec  = Option.when(io.readVlState.isDefined )(Wire(Vec(numVlStateRead, SrcState())))
+  private val vlSrcIsZeroVec  = Option.when(io.readVlInfo.isDefined )(Wire(Vec(numVlStateRead, Bool())))
+  private val vlSrcIsVlMaxVec  = Option.when(io.readVlInfo.isDefined )(Wire(Vec(numVlStateRead, Bool())))
   private val intAllSrcStateVec = Option.when(io.readIntState.isDefined)(Wire(Vec(numIn * numRegSrc, SrcState())))
   private val fpAllSrcStateVec  = Option.when(io.readFpState.isDefined )(Wire(Vec(numIn * numRegSrc, SrcState())))
   private val vecAllSrcStateVec = Option.when(io.readVfState.isDefined )(Wire(Vec(numIn * numRegSrc, SrcState())))
@@ -204,6 +207,8 @@ abstract class Dispatch2IqImp(override val wrapper: Dispatch2Iq)(implicit p: Par
 
     io.readVlState.get.map(_.req).zip(vlReqPsrcVec).foreach(x => x._1 := x._2)
     io.readVlState.get.map(_.resp).zip(vlSrcStateVec.get).foreach(x => x._2 := x._1)
+    io.readVlInfo.get.map(_.is_zero).zip(vlSrcIsZeroVec.get).foreach(x => x._2 := x._1)
+    io.readVlInfo.get.map(_.is_vlmax).zip(vlSrcIsVlMaxVec.get).foreach(x => x._2 := x._1)
     io.readVlState.get.map(_.loadDependency).zip(vlSrcLoadDependency.get).foreach(x => x._2 := x._1)
 
     for (i <- 0 until numIn) {
@@ -215,6 +220,31 @@ abstract class Dispatch2IqImp(override val wrapper: Dispatch2Iq)(implicit p: Par
       vecAllSrcStateVec.get(i * numRegSrc + numRegSrc - 1)       := vlSrcStateVec.get(i);
       vecAllSrcLoadDependency.get(i * numRegSrc + numRegSrc - 2) := v0SrcLoadDependency.get(i);
       vecAllSrcLoadDependency.get(i * numRegSrc + numRegSrc - 1) := vlSrcLoadDependency.get(i);
+
+      // same as eliminate the old vd dependency in issue queue when wake up by wakeup
+      val isDependOldVd = io.in(i).bits.vpu.isDependOldVd
+      val isWritePartVd = io.in(i).bits.vpu.isWritePartVd
+      val vta = io.in(i).bits.vpu.vta
+      val vma = io.in(i).bits.vpu.vma
+      val vm = io.in(i).bits.vpu.vm
+      val vlIsVlmax = vlSrcIsVlMaxVec.get(i)
+      val vlIsZero = vlSrcIsZeroVec.get(i)
+      val vlIsNonZero = !vlSrcIsZeroVec.get(i)
+      val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd
+      val ignoreWhole = (vm =/= 0.U || vma) && vta
+      val isFof = VlduType.isFof(io.in(i).bits.fuOpType)
+      for (j <- 0 until numRegSrcVf) {
+        val ignoreOldVd = Wire(Bool())
+        if (j == numRegSrcVf - 1) {
+          // check whether can ignore the old vd dependency
+          ignoreOldVd := SrcState.isReady(vlSrcStateVec.get(i)) && !isFof && vlIsNonZero && !isDependOldVd && (ignoreTail || ignoreWhole)
+        } else {
+          // check whether can ignore the src
+          ignoreOldVd := false.B
+        }
+        uopsIn(i).bits.srcType(j) := Mux(ignoreOldVd, SrcType.no, io.in(i).bits.srcType(j))
+        vecAllSrcStateVec.get(i * numRegSrc + j) := Mux(ignoreOldVd, SrcState.rdy, vfSrcStateVec.get(i * numRegSrcVf + j))
+      }
     }
   }
   if (io.readRCTagTableState.isDefined) {

src/main/scala/xiangshan/backend/issue/EntryBundles.scala

@@ -208,10 +208,12 @@ object EntryBundles extends HasCircularQueuePtrHelper {
       })
       var numVecWb = params.backendParam.getVfWBExeGroup.size
       var numV0Wb = params.backendParam.getV0WBExeGroup.size
+      var intSchdVlWbPort = p(XSCoreParamsKey).intSchdVlWbPort
+      var vfSchdVlWbPort = p(XSCoreParamsKey).vfSchdVlWbPort
       // int wb is first bit of vlwb, which is after vfwb and v0wb
-      common.vlWakeupByIntWb  := wakeUpFromVl(numVecWb + numV0Wb)
+      common.vlWakeupByIntWb  := wakeUpFromVl(numVecWb + numV0Wb + intSchdVlWbPort)
       // vf wb is second bit of wb
-      common.vlWakeupByVfWb   := wakeUpFromVl(numVecWb + numV0Wb + 1)
+      common.vlWakeupByVfWb   := wakeUpFromVl(numVecWb + numV0Wb + vfSchdVlWbPort)
     } else {
       common.vlWakeupByIntWb  := false.B
       common.vlWakeupByVfWb   := false.B
@@ -298,7 +300,7 @@ object EntryBundles extends HasCircularQueuePtrHelper {
       val ignoreOldVd = Wire(Bool())
       val vlWakeUpByIntWb = common.vlWakeupByIntWb
       val vlWakeUpByVfWb = common.vlWakeupByVfWb
-      val isDependOldvd = entryReg.payload.vpu.isDependOldvd
+      val isDependOldVd = entryReg.payload.vpu.isDependOldVd
       val isWritePartVd = entryReg.payload.vpu.isWritePartVd
       val vta = entryReg.payload.vpu.vta
       val vma = entryReg.payload.vpu.vma
@@ -319,7 +321,7 @@ object EntryBundles extends HasCircularQueuePtrHelper {
           * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value
           * 3. when vl = vlmax, we can set srctype to imm when vta is not set
           */
-        ignoreOldVd := !VlduType.isFof(entryReg.payload.fuOpType) && srcIsVec && vlIsNonZero && !isDependOldvd && (ignoreTail || ignoreWhole)
+        ignoreOldVd := !VlduType.isFof(entryReg.payload.fuOpType) && srcIsVec && vlIsNonZero && !isDependOldVd && (ignoreTail || ignoreWhole)
       } else {
         ignoreOldVd := false.B
       }

src/main/scala/xiangshan/backend/issue/Scheduler.scala

@@ -12,7 +12,7 @@ import xiangshan.backend.datapath.DataConfig._
 import xiangshan.backend.datapath.WbConfig._
 import xiangshan.backend.fu.FuType
 import xiangshan.backend.regfile.RfWritePortWithConfig
-import xiangshan.backend.rename.BusyTable
+import xiangshan.backend.rename.{BusyTable, VlBusyTable}
 import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr}
 import xiangshan.backend.datapath.WbConfig.V0WB
 import xiangshan.backend.regfile.VlPregParams
@@ -185,7 +185,7 @@ abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockPa
     case _ => None
   }
   val vlBusyTable = schdType match {
-    case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVlStateRead, wrapper.numVlStateWrite, VlPhyRegs, VlWB())))
+    case VfScheduler() | MemScheduler() => Some(Module(new VlBusyTable(dispatch2Iq.numVlStateRead, wrapper.numVlStateWrite, VlPhyRegs, VlWB())))
     case _ => None
   }
 
@@ -203,6 +203,7 @@ abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockPa
     dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read)
     dp2iq.readV0State.foreach(_ <> v0BusyTable.get.io.read)
     dp2iq.readVlState.foreach(_ <> vlBusyTable.get.io.read)
+    dp2iq.readVlInfo.foreach(_ <> vlBusyTable.get.io_vl_read.vlReadInfo)
     dp2iq.readRCTagTableState.foreach(_ <> rcTagTable.get.io.readPorts)
   }
 
@@ -283,6 +284,8 @@ abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockPa
       bt.io.wakeUp := io.fromSchedulers.wakeupVec
       bt.io.og0Cancel := io.fromDataPath.og0Cancel
       bt.io.ldCancel := io.ldCancel
+
+      bt.io_vl_Wb.vlWriteBackInfo := io.vlWriteBackInfo
     case None =>
   }