Zvbb: fix wrong result location for vclz.v and vctz.v

OpenXiangShan · May 24, 2024 · 86353a7 · 86353a7
1 parent 84ddc1a
commit 86353a7
Showing 1 changed file with 9 additions and 9 deletions.
diff --git a/src/main/scala/yunsuan/vector/VectorALU/VIntMisc64b.scala b/src/main/scala/yunsuan/vector/VectorALU/VIntMisc64b.scala
@@ -297,9 +297,9 @@ class VIntMisc64b extends Module {
   val pop_32 = Wire(Vec(2, UInt(32.W)))
   val pop_64 = Wire(Vec(1, UInt(64.W)))
   val cnt8  = Wire(Vec(8, UInt(8.W)))
-  val cnt16 = Wire(Vec(4, UInt(8.W)))
-  val cnt32 = Wire(Vec(2, UInt(8.W)))
-  val cnt64 = Wire(Vec(1, UInt(8.W)))
+  val cnt16 = Wire(Vec(4, UInt(16.W)))
+  val cnt32 = Wire(Vec(2, UInt(32.W)))
+  val cnt64 = Wire(Vec(1, UInt(64.W)))
 
   pop_8 := vs2.asTypeOf(pop_8)
   pop_16 := vs2.asTypeOf(pop_16)
@@ -316,7 +316,7 @@ class VIntMisc64b extends Module {
         eewVd.is16,
       ),
       Seq(
-        Mux(opcode.isClz, vs2(8*i+7+32,8*i+32) << 8, VecInit((vs2(8*i+7+32,8*i+32) << 8).asBools.reverse).asUInt) | (1.U << 7),
+        Mux(opcode.isClz, vs2(8*i+7+32,8*i+32) << 8, VecInit(vs2(8*i+7+32,8*i+32).asBools.reverse).asUInt << 8) | (1.U << 7),
         Mux(opcode.isClz, vs2(16*i+15,16*i), VecInit(vs2(16*i+15,16*i).asBools.reverse).asUInt),
       )
     )
@@ -329,8 +329,8 @@ class VIntMisc64b extends Module {
       eewVd.is32,
     ),
     Seq(
-      Mux(opcode.isClz, vs2(55, 48) << 24, VecInit((vs2(55, 48) << 24).asBools.reverse).asUInt) | (1.U << 23),
-      Mux(opcode.isClz, vs2(47, 32) << 16, VecInit((vs2(47, 32) << 16).asBools.reverse).asUInt) | (1.U << 15),
+      Mux(opcode.isClz, vs2(55, 48) << 24, VecInit(vs2(55, 48).asBools.reverse).asUInt << 24) | (1.U << 23),
+      Mux(opcode.isClz, vs2(47, 32) << 16, VecInit(vs2(47, 32).asBools.reverse).asUInt << 16) | (1.U << 15),
       Mux(opcode.isClz, vs2(31, 0), VecInit(vs2(31, 0).asBools.reverse).asUInt),
     )
   )
@@ -342,9 +342,9 @@ class VIntMisc64b extends Module {
       eewVd.is64,
     ),
     Seq(
-      Mux(opcode.isClz, vs2(63, 56) << 56, VecInit((vs2(63, 56) << 56).asBools.reverse).asUInt) | (1.U << 55),
-      Mux(opcode.isClz, vs2(63, 48) << 48, VecInit((vs2(63, 48) << 48).asBools.reverse).asUInt) | (1.U << 47),
-      Mux(opcode.isClz, vs2(63, 32) << 32, VecInit((vs2(63, 32) << 32).asBools.reverse).asUInt) | (1.U << 31),
+      Mux(opcode.isClz, vs2(63, 56) << 56, VecInit(vs2(63, 56).asBools.reverse).asUInt << 56) | (1.U << 55),
+      Mux(opcode.isClz, vs2(63, 48) << 48, VecInit(vs2(63, 48).asBools.reverse).asUInt << 48) | (1.U << 47),
+      Mux(opcode.isClz, vs2(63, 32) << 32, VecInit(vs2(63, 32).asBools.reverse).asUInt << 32) | (1.U << 31),
       Mux(opcode.isClz, vs2, VecInit(vs2.asBools.reverse).asUInt),
     )
   )