fpu: remove some import

OpenXiangShan · Apr 29, 2024 · daed502 · daed502
1 parent 4390701
commit daed502
Show file tree

Hide file tree

Showing 4 changed files with 0 additions and 4 deletions.
diff --git a/src/main/scala/yunsuan/fpu/FloatAdder.scala b/src/main/scala/yunsuan/fpu/FloatAdder.scala
@@ -1,6 +1,5 @@
 package yunsuan.fpu
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util._
 import yunsuan.vector._
 import yunsuan.{FaddOpCode, VectorElementFormat}

diff --git a/src/main/scala/yunsuan/fpu/FloatFMA.scala b/src/main/scala/yunsuan/fpu/FloatFMA.scala
@@ -1,6 +1,5 @@
 package yunsuan.fpu
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util._
 import yunsuan.FmaOpCode
 import yunsuan.util.GatedValidRegNext

diff --git a/src/main/scala/yunsuan/fpulite/FloatAdder.scala b/src/main/scala/yunsuan/fpulite/FloatAdder.scala
@@ -1,6 +1,5 @@
 package yunsuan.fpulite
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util._
 import yunsuan.vector._
 import yunsuan.{VfaddOpCode, VectorElementFormat}

diff --git a/src/main/scala/yunsuan/fpulite/FloatFMA.scala b/src/main/scala/yunsuan/fpulite/FloatFMA.scala
@@ -1,6 +1,5 @@
 package yunsuan.fpulite
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util._
 import yunsuan.FmaOpCode
 import yunsuan.util.GatedValidRegNext