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fpu: remove some import #128

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merged 1 commit into from
Apr 29, 2024
Merged

fpu: remove some import #128

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1 change: 0 additions & 1 deletion src/main/scala/yunsuan/fpu/FloatAdder.scala
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Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
package yunsuan.fpu
import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import chisel3.util._
import yunsuan.vector._
import yunsuan.{FaddOpCode, VectorElementFormat}
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1 change: 0 additions & 1 deletion src/main/scala/yunsuan/fpu/FloatFMA.scala
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Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
package yunsuan.fpu
import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import chisel3.util._
import yunsuan.FmaOpCode
import yunsuan.util.GatedValidRegNext
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1 change: 0 additions & 1 deletion src/main/scala/yunsuan/fpulite/FloatAdder.scala
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Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
package yunsuan.fpulite
import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import chisel3.util._
import yunsuan.vector._
import yunsuan.{VfaddOpCode, VectorElementFormat}
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1 change: 0 additions & 1 deletion src/main/scala/yunsuan/fpulite/FloatFMA.scala
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Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
package yunsuan.fpulite
import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import chisel3.util._
import yunsuan.FmaOpCode
import yunsuan.util.GatedValidRegNext
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