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@PedroAntunes178
PedroAntunes178 committed Dec 29, 2023
2 parents 6acd37e + 59fb43a commit 3937a20
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46 changes: 1 addition & 45 deletions hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v
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Original file line number Diff line number Diff line change
Expand Up @@ -165,41 +165,7 @@ module iob_soc_fpga_wrapper (
.memory_mem_dqs_n (ddr3b_dqs_n),
.memory_mem_odt (ddr3b_odt),

.axi_bridge_0_s0_awid (memory_axi_awid),
.axi_bridge_0_s0_awaddr (memory_axi_awaddr),
.axi_bridge_0_s0_awlen (memory_axi_awlen),
.axi_bridge_0_s0_awsize (memory_axi_awsize),
.axi_bridge_0_s0_awburst(memory_axi_awburst),
.axi_bridge_0_s0_awlock (memory_axi_awlock),
.axi_bridge_0_s0_awcache(memory_axi_awcache),
.axi_bridge_0_s0_awprot (memory_axi_awprot),
.axi_bridge_0_s0_awvalid(memory_axi_awvalid),
.axi_bridge_0_s0_awready(memory_axi_awready),
.axi_bridge_0_s0_wdata (memory_axi_wdata),
.axi_bridge_0_s0_wstrb (memory_axi_wstrb),
.axi_bridge_0_s0_wlast (memory_axi_wlast),
.axi_bridge_0_s0_wvalid (memory_axi_wvalid),
.axi_bridge_0_s0_wready (memory_axi_wready),
.axi_bridge_0_s0_bid (memory_axi_bid),
.axi_bridge_0_s0_bresp (memory_axi_bresp),
.axi_bridge_0_s0_bvalid (memory_axi_bvalid),
.axi_bridge_0_s0_bready (memory_axi_bready),
.axi_bridge_0_s0_arid (memory_axi_arid),
.axi_bridge_0_s0_araddr (memory_axi_araddr),
.axi_bridge_0_s0_arlen (memory_axi_arlen),
.axi_bridge_0_s0_arsize (memory_axi_arsize),
.axi_bridge_0_s0_arburst(memory_axi_arburst),
.axi_bridge_0_s0_arlock (memory_axi_arlock),
.axi_bridge_0_s0_arcache(memory_axi_arcache),
.axi_bridge_0_s0_arprot (memory_axi_arprot),
.axi_bridge_0_s0_arvalid(memory_axi_arvalid),
.axi_bridge_0_s0_arready(memory_axi_arready),
.axi_bridge_0_s0_rid (memory_axi_rid),
.axi_bridge_0_s0_rdata (memory_axi_rdata),
.axi_bridge_0_s0_rresp (memory_axi_rresp),
.axi_bridge_0_s0_rlast (memory_axi_rlast),
.axi_bridge_0_s0_rvalid (memory_axi_rvalid),
.axi_bridge_0_s0_rready (memory_axi_rready),
`include "iob_soc_cyclonev_interconnect_s_portmap.vs"

.mem_if_ddr3_emif_0_pll_sharing_pll_mem_clk (),
.mem_if_ddr3_emif_0_pll_sharing_pll_write_clk (),
Expand All @@ -224,14 +190,4 @@ module iob_soc_fpga_wrapper (
);
`endif

`ifdef IOB_SOC_USE_EXTMEM
// interconnect clk and arst
wire clk_interconnect;
wire arst_interconnect;
assign clk_interconnect = clk;
assign arst_interconnect = arst;
`endif

`include "iob_soc_interconnect.vs"

endmodule
1 change: 1 addition & 0 deletions iob_soc.py
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@ class iob_soc(iob_module):
name = "iob_soc"
version = "V0.70"
setup_dir = os.path.dirname(__file__)
rw_overlap = True

# IOb-SoC has the following list of non standard attributes:
peripherals = None # List with instances peripherals to include in system
Expand Down
205 changes: 205 additions & 0 deletions scripts/iob_soc_create_wrapper_files.py
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Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,11 @@ def create_wrapper_files(build_dir, name, ios, confs, num_extmem_connections):
fd_pportmaps.close()

create_interconnect_instance(out_dir, name, num_extmem_connections)
create_cyclonev_interconnect_s_portmap(out_dir, name, num_extmem_connections)
modify_alt_ddr3_qsys(
os.path.join(build_dir, f"hardware/fpga/quartus/CYCLONEV-GT-DK/alt_ddr3.qsys"),
num_extmem_connections,
)
create_ku040_interconnect_s_portmap(out_dir, name, num_extmem_connections)
create_ku040_rstn(out_dir, name, num_extmem_connections)

Expand Down Expand Up @@ -284,3 +289,203 @@ def create_ku040_interconnect_s_portmap(out_dir, name, num_extmem_connections):
fp_interconnect = open(f"{out_dir}/{name}_ku040_interconnect_s_portmap.vs", "w")
fp_interconnect.write(interconnect_str)
fp_interconnect.close()


def create_cyclonev_interconnect_s_portmap(out_dir, name, num_extmem_connections):
interconnect_str = ""
for i in range(num_extmem_connections):
interconnect_str += f"""
//
// External memory connection {i}
//
//Write address
.axi_bridge_{i}_s0_awid (axi_awid[{i}*AXI_ID_W+:1]),
.axi_bridge_{i}_s0_awaddr (axi_awaddr[{i}*AXI_ADDR_W+:AXI_ADDR_W]),
.axi_bridge_{i}_s0_awlen (axi_awlen[{i}*AXI_LEN_W+:AXI_LEN_W]),
.axi_bridge_{i}_s0_awsize (axi_awsize[{i}*3+:3]),
.axi_bridge_{i}_s0_awburst(axi_awburst[{i}*2+:2]),
.axi_bridge_{i}_s0_awlock (axi_awlock[{i}*2+:1]),
.axi_bridge_{i}_s0_awcache(axi_awcache[{i}*4+:4]),
.axi_bridge_{i}_s0_awprot (axi_awprot[{i}*3+:3]),
.axi_bridge_{i}_s0_awvalid(axi_awvalid[{i}*1+:1]),
.axi_bridge_{i}_s0_awready(axi_awready[{i}*1+:1]),
//Write data
.axi_bridge_{i}_s0_wdata (axi_wdata[{i}*AXI_DATA_W+:AXI_DATA_W]),
.axi_bridge_{i}_s0_wstrb (axi_wstrb[{i}*(AXI_DATA_W/8)+:(AXI_DATA_W/8)]),
.axi_bridge_{i}_s0_wlast (axi_wlast[{i}*1+:1]),
.axi_bridge_{i}_s0_wvalid (axi_wvalid[{i}*1+:1]),
.axi_bridge_{i}_s0_wready (axi_wready[{i}*1+:1]),
//Write response
.axi_bridge_{i}_s0_bid (axi_bid[{i}*AXI_ID_W+:1]),
.axi_bridge_{i}_s0_bresp (axi_bresp[{i}*2+:2]),
.axi_bridge_{i}_s0_bvalid (axi_bvalid[{i}*1+:1]),
.axi_bridge_{i}_s0_bready (axi_bready[{i}*1+:1]),
//Read address
.axi_bridge_{i}_s0_arid (axi_arid[{i}*AXI_ID_W+:1]),
.axi_bridge_{i}_s0_araddr (axi_araddr[{i}*AXI_ADDR_W+:AXI_ADDR_W]),
.axi_bridge_{i}_s0_arlen (axi_arlen[{i}*AXI_LEN_W+:AXI_LEN_W]),
.axi_bridge_{i}_s0_arsize (axi_arsize[{i}*3+:3]),
.axi_bridge_{i}_s0_arburst(axi_arburst[{i}*2+:2]),
.axi_bridge_{i}_s0_arlock (axi_arlock[{i}*2+:1]),
.axi_bridge_{i}_s0_arcache(axi_arcache[{i}*4+:4]),
.axi_bridge_{i}_s0_arprot (axi_arprot[{i}*3+:3]),
.axi_bridge_{i}_s0_arvalid(axi_arvalid[{i}*1+:1]),
.axi_bridge_{i}_s0_arready(axi_arready[{i}*1+:1]),
//Read data
.axi_bridge_{i}_s0_rid (axi_rid[{i}*AXI_ID_W+:1]),
.axi_bridge_{i}_s0_rdata (axi_rdata[{i}*AXI_DATA_W+:AXI_DATA_W]),
.axi_bridge_{i}_s0_rresp (axi_rresp[{i}*2+:2]),
.axi_bridge_{i}_s0_rlast (axi_rlast[{i}*1+:1]),
.axi_bridge_{i}_s0_rvalid (axi_rvalid[{i}*1+:1]),
.axi_bridge_{i}_s0_rready (axi_rready[{i}*1+:1]),
"""

fp_interconnect = open(f"{out_dir}/{name}_cyclonev_interconnect_s_portmap.vs", "w")
fp_interconnect.write(interconnect_str)
fp_interconnect.close()


# Add slave ports to alt_ddr3.qsys, based on number of extmem connections
def modify_alt_ddr3_qsys(qsys_path, num_extmem_connections):
with open(qsys_path, "r") as f:
lines = f.readlines()
new_lines = []

for line in lines:
new_lines.append(line)
if "element clk_0" in line:
for i in range(1, num_extmem_connections):
new_lines.insert(-1,
f"""
element axi_bridge_{i}
{{
datum _sortIndex
{{
value = "{i+2}";
type = "int";
}}
}}
\n""",
)
elif 'interface name="clk"' in line:
for i in range(1, num_extmem_connections):
new_lines.insert(-1,
f"""
<interface
name="axi_bridge_{i}_s0"
internal="axi_bridge_{i}.s0"
type="axi4"
dir="end" />
\n""",
)
elif 'module name="clk_0"' in line:
for i in range(1, num_extmem_connections):
new_lines.insert(-1,
f"""
<module
name="axi_bridge_{i}"
kind="altera_axi_bridge"
version="20.1"
enabled="1">
<parameter name="ADDR_WIDTH" value="28" />
<parameter name="AXI_VERSION" value="AXI4" />
<parameter name="COMBINED_ACCEPTANCE_CAPABILITY" value="16" />
<parameter name="COMBINED_ISSUING_CAPABILITY" value="16" />
<parameter name="DATA_WIDTH" value="32" />
<parameter name="M0_ID_WIDTH" value="1" />
<parameter name="READ_ACCEPTANCE_CAPABILITY" value="16" />
<parameter name="READ_ADDR_USER_WIDTH" value="64" />
<parameter name="READ_DATA_REORDERING_DEPTH" value="1" />
<parameter name="READ_DATA_USER_WIDTH" value="64" />
<parameter name="READ_ISSUING_CAPABILITY" value="16" />
<parameter name="S0_ID_WIDTH" value="1" />
<parameter name="USE_M0_ARBURST" value="1" />
<parameter name="USE_M0_ARCACHE" value="1" />
<parameter name="USE_M0_ARID" value="1" />
<parameter name="USE_M0_ARLEN" value="1" />
<parameter name="USE_M0_ARLOCK" value="1" />
<parameter name="USE_M0_ARQOS" value="0" />
<parameter name="USE_M0_ARREGION" value="0" />
<parameter name="USE_M0_ARSIZE" value="1" />
<parameter name="USE_M0_ARUSER" value="0" />
<parameter name="USE_M0_AWBURST" value="1" />
<parameter name="USE_M0_AWCACHE" value="1" />
<parameter name="USE_M0_AWID" value="1" />
<parameter name="USE_M0_AWLEN" value="1" />
<parameter name="USE_M0_AWLOCK" value="1" />
<parameter name="USE_M0_AWQOS" value="0" />
<parameter name="USE_M0_AWREGION" value="0" />
<parameter name="USE_M0_AWSIZE" value="1" />
<parameter name="USE_M0_AWUSER" value="0" />
<parameter name="USE_M0_BID" value="1" />
<parameter name="USE_M0_BRESP" value="1" />
<parameter name="USE_M0_BUSER" value="0" />
<parameter name="USE_M0_RID" value="1" />
<parameter name="USE_M0_RLAST" value="1" />
<parameter name="USE_M0_RRESP" value="1" />
<parameter name="USE_M0_RUSER" value="0" />
<parameter name="USE_M0_WSTRB" value="1" />
<parameter name="USE_M0_WUSER" value="0" />
<parameter name="USE_PIPELINE" value="1" />
<parameter name="USE_S0_ARCACHE" value="1" />
<parameter name="USE_S0_ARLOCK" value="1" />
<parameter name="USE_S0_ARPROT" value="1" />
<parameter name="USE_S0_ARQOS" value="0" />
<parameter name="USE_S0_ARREGION" value="0" />
<parameter name="USE_S0_ARUSER" value="0" />
<parameter name="USE_S0_AWCACHE" value="1" />
<parameter name="USE_S0_AWLOCK" value="1" />
<parameter name="USE_S0_AWPROT" value="1" />
<parameter name="USE_S0_AWQOS" value="0" />
<parameter name="USE_S0_AWREGION" value="0" />
<parameter name="USE_S0_AWUSER" value="0" />
<parameter name="USE_S0_BRESP" value="1" />
<parameter name="USE_S0_BUSER" value="0" />
<parameter name="USE_S0_RRESP" value="1" />
<parameter name="USE_S0_RUSER" value="0" />
<parameter name="USE_S0_WLAST" value="1" />
<parameter name="USE_S0_WUSER" value="0" />
<parameter name="WRITE_ACCEPTANCE_CAPABILITY" value="16" />
<parameter name="WRITE_ADDR_USER_WIDTH" value="64" />
<parameter name="WRITE_DATA_USER_WIDTH" value="64" />
<parameter name="WRITE_ISSUING_CAPABILITY" value="16" />
<parameter name="WRITE_RESP_USER_WIDTH" value="64" />
</module>
\n""",
)
elif 'end="axi_bridge_0.clk"' in line:
for i in range(1, num_extmem_connections):
new_lines.insert(-1,
f"""
<connection
kind="avalon"
version="20.1"
start="axi_bridge_{i}.m0"
end="mem_if_ddr3_emif_0.avl">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="clock" version="20.1" start="clk_0.clk" end="axi_bridge_{i}.clk" />
\n""",
)
elif 'name="qsys_mm.clockCrossingAdapter"' in line:
for i in range(1, num_extmem_connections):
new_lines.insert(-1,
f"""
<connection
kind="reset"
version="20.1"
start="clk_0.clk_reset"
end="axi_bridge_{i}.clk_reset" />
\n""",
)

with open(qsys_path, "w") as f:
f.writelines(new_lines)
3 changes: 2 additions & 1 deletion scripts/iob_soc_utils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -192,7 +192,6 @@ def post_setup_iob_soc(python_module, num_extmem_connections):
name = python_module.name

# Run iob-soc specialized setup sequence
iob_soc_wrapper_setup(python_module, num_extmem_connections)
iob_soc_sw_setup(python_module)
iob_soc_hw_setup(python_module)
iob_soc_doc_setup(python_module)
Expand All @@ -201,6 +200,8 @@ def post_setup_iob_soc(python_module, num_extmem_connections):
return
### Only run lines below if this system is the top module ###

iob_soc_wrapper_setup(python_module, num_extmem_connections)

# Check if was setup with INIT_MEM and USE_EXTMEM (check if macro exists)
extmem_macro = bool(
next((i["val"] for i in confs if i["name"] == "USE_EXTMEM"), False)
Expand Down
1 change: 1 addition & 0 deletions submodules/LIB/hardware/modules/fifo/iob_fifo_async/hardware/src/iob_fifo_async.v
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Original file line number Diff line number Diff line change
Expand Up @@ -215,6 +215,7 @@ module iob_fifo_async #(
.clk_i (r_clk_i),
.cke_i (r_cke_i),
.arst_i (r_arst_i),
.rst_i (r_rst_i),
.w_addr_i (w_addr),
.w_en_i (w_en_int),
.w_data_i (w_data_i),
Expand Down
9 changes: 5 additions & 4 deletions submodules/LIB/hardware/modules/fifo/iob_fifo_sync/hardware/src/iob_fifo_sync.v
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Original file line number Diff line number Diff line change
Expand Up @@ -117,25 +117,25 @@ module iob_fifo_sync #(
//FIFO empty
wire r_empty_nxt;
assign r_empty_nxt = level_nxt < {1'b0,R_INCR};
iob_reg #(
iob_reg_r #(
.DATA_W (1),
.RST_VAL(1'd1)
) r_empty_reg0 (
`include "clk_en_rst_s_s_portmap.vs"

.rst_i(rst_i),
.data_i(r_empty_nxt),
.data_o(r_empty_o)
);

//FIFO full
wire w_full_nxt;
assign w_full_nxt = level_nxt > (FIFO_SIZE - W_INCR);
iob_reg #(
iob_reg_r #(
.DATA_W (1),
.RST_VAL(1'd0)
) w_full_reg0 (
`include "clk_en_rst_s_s_portmap.vs"

.rst_i(rst_i),
.data_i(w_full_nxt),
.data_o(w_full_o)
);
Expand All @@ -154,6 +154,7 @@ module iob_fifo_sync #(
.ext_mem_r_addr_o(ext_mem_r_addr_o),
.ext_mem_r_data_i(ext_mem_r_data_i),
`include "clk_en_rst_s_s_portmap.vs"
.rst_i(rst_i),
.w_addr_i (w_addr),
.w_en_i (w_en_int),
.w_data_i (w_data_i),
Expand Down
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