Skip to content
View ShichenQiao's full-sized avatar

Organizations

@riscv-hdc

Block or report ShichenQiao

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
ShichenQiao/README.md

Hi! 👋 My name is Shichen "Justin" Qiao and I'm a Master's student at UC Berkeley EECS!

languages graph streak graph

python logo cplusplus logo c logo java logo sqlite logo git logo pytorch logo unity logo ubuntu logo vscode logo


Snake animation

Pinned Loading

  1. ECE554_SP23_FPGA_Handwriting_Recognition ECE554_SP23_FPGA_Handwriting_Recognition Public archive

    Senior Design Project at UW-Madison ECE

    Verilog 10

  2. ECE551_FA2021_Knights_Tour ECE551_FA2021_Knights_Tour Public archive

    Final project repo of ECE551 in Fall 2021 at UW Madison. Owned by Team Doraemon.

    SystemVerilog 1

  3. ECE552_WISC-SP22_RISC_Processor ECE552_WISC-SP22_RISC_Processor Public archive

    UW-Madison ECE 552 class project by Shichen (Justin) Qiao and Xin (Cassie) Su

    Verilog 1

  4. Alfalfa_Database Alfalfa_Database Public archive

    Scripts involved in the development of Alfalfa Databases' SQLite database file, Flask web application, and command-line-based Java application.

    HTML 1

  5. ECE353_SP21_Breaker ECE353_SP21_Breaker Public archive

    Contributors: Justin Qiao and Mark Xia

    C

  6. HDLBits_Solutions HDLBits_Solutions Public archive

    Shichen Qiao's solutions to all Verilog problems on https://hdlbits.01xz.net/

    SystemVerilog