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[CPCHawk] Update readme
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Asnivor committed Oct 2, 2024
1 parent 4a8340c commit 016ab15
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Expand Up @@ -96,7 +96,7 @@ public virtual byte PushBus()
public abstract void InitROM(RomData[] romData);

/// <summary>
/// ULA reads the memory at the specified address
/// Gate Array reads the memory at the specified address
/// (No memory contention)
/// </summary>
public virtual byte FetchScreenMemory(ushort addr)
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53 changes: 41 additions & 12 deletions src/BizHawk.Emulation.Cores/Computers/AmstradCPC/readme.md
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@@ -1,8 +1,8 @@
## CPCHawk
# CPCHawk

Work has started up again as of Sep2024.

#### In Place
## In Place
* CPC464, CPC6128 (default)
* Port IO decoding
* i8255 Programmable Peripheral Interface (PPI) chip emulation
Expand All @@ -11,35 +11,46 @@ Work has started up again as of Sep2024.
* FDC and FDD devices
* .DSK image parsing and identification (to auto differenciate from ZX Spectrum disk bootloader)

#### Right now
## Right now
* Gate array implementation undergoing a full re-write
* CRTC implementations are being re-written (based on https://shaker.logonsystem.eu/ACCC1.8-EN.pdf)
* CRT screen emulation in progress
* Amstrad Gate Array chip emulation
* Z80 timing verification

#### Future..
## Future..
* CPC664, CPC464plus, CPC6128plus, GX4000 models
* Expansion IO
* Working Datacorder (tape) emulation and handling of .CDT files
* Memory expansions
* External peripherals (Speech Synthesizers etc..)
* Optimisation of EVERYTHING

#### Known Issues
## Known Issues
* Lots of things

#### References in use
## References in use
* https://shaker.logonsystem.eu/ACCC1.8-EN.pdf
* https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/need-plustest-dsk-testbench-9-output-on-original-cpc-6128/

#### Test suites
* http://www.winape.net/download/plustest.zip
* https://shaker.logonsystem.eu/shaker26.dsk
## Test suites


#### Current test issues
##### PlusTest - Test 5 - Instruction timing test (current failures)
### WinAPU PlusTest (http://www.winape.net/download/plustest.zip)

#### Test 1: ASIC Sprite test
Plus models and GX4000 only - awaiting implementation

#### Test 2: Monitor HSYNC test
Failing

#### Test 3: Horizontal Split and Soft-Scroll test
Failing

#### Test 4: Interrupt, VSync and R52 timing test
Unknown

#### Test 5: Instruction timing test

| Prefix | OPC | Inst. | Comments |
|:----:|:----:|:-----:|:------------:|
Expand All @@ -65,11 +76,29 @@ Work has started up again as of Sep2024.
|DD CB| D3:5| SET 2, (ix+d), e | |
|DD CB| DB:5| SET 3, (ix+d), e | |

..to be continued
Everything else passes. Almost certainly the problems observed relate to IO timing.

#### Test 6: Register 0 test
Unknown

#### Test 7: Register 4 test
Unknown

#### Test 8: Register 9 test
Unknown

#### Test 9: Interrupt Wait test



### Amstrad Diagnostics (https://github.com/llopis/amstrad-diagnostics)

Program stalls. Likely because the firmware vertical flyback checks are not happening at the right time.
Might be fixed when port timing is correct.


### Shaker Tests (https://shaker.logonsystem.eu/shaker26.dsk)

Need to correct CRTC emulation and port access timing before even attempting these.

-Asnivor

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