# EASIROC_firmware

…or create a new repository on the command line  

echo "# EASIROC_firmware" >> README.md  
git init  
git add README.md  
# (use "git add/rm <file>..." to update what will be committed)
git commit -m "commit 20/03/31"  
git remote add origin https://github.com/TomohisaOgawa/EASIROC_firmware.git  
git push -u origin master  

…or push an existing repository from the command line  

git remote add origin https://github.com/TomohisaOgawa/EASIROC_firmware.git  
git push -u origin master  

if you remove .git  
git pull origin master


written @ 21/10/20
need to generate tokens to git push, commit, etc 
https://docs.github.com/ja/authentication/keeping-your-account-and-data-secure/creating-a-personal-access-token

git status
git add .
git commit -m "commit 21/09/01 document"
git remote add origin https://github.com/TomohisaOgawa/EASIROC_firmware.git
git push -u origin master

========== EASIROC_firmware_NC150923_viva14.3_work2009.Fixed200901 
written @ 21/10/20

-. Implement internal generation of Stop and Accept pulses.
   (the Chikuma model needs to split a trigger signal in NIMs, apply a delay, etc., 
    and those puleses need to input into the module.)   
-. Change Hold timing from software (the Chikuma model needs to adjust it in NIMs)
-. 3 patterns of test pulse signal amplitude (Chikuma model has 1 pattern only)
-. External trigger input is available
-. Freeze during data acquisition due to a bug of pulse delay in the firmware was solved,
   which is discovered by Sato.

Those above were implemented for the MPPC mass test of SFGD, 
and it works fine on the actual module level.


========== 2020/01/01 EASIROCfirmware_NC150923  
written @ 20/07/01

the first version by Naruhiro Chikuma  : NC

-. injection pattern of test charge is added   
        when "001" =>  1   
           CAL1 <= 'Z'; -- High Impedance    
           CAL2 <= test_palse;   
        when "010" =>  2   
           CAL1 <= test_palse;   
           CAL2 <= test_palse;  
        when others => 0   
           CAL1 <= test_palse;   
           CAL2 <= 'Z'; -- High Impedance   

see yaml/RegisterValue.yml

# select combination of calibartion pulse    
# this was confirmed @ 19/12/30    
TestChargePtn: 0   
Trigger:   
      # Explanation of parameters below   
      # 1: The default operation:   
      #     By adjusting Trig, one needs to put HOLD, STOP, & ACCEPT individually.  
      # 2: Semi-internal trigger:  
      #     By adjusting Trig, one needs to input HOLD. STOP & ACCEPT are internally generated.   
      # 3: All-internal trigger:  
      #     Based on logic Trig, all three pulses: HOLD, STOP, & ACCEPT are internally generated.   
      Mode: 3  
      DelayTrigger: 10 # Adjustable delay with the internal 250 MHz CLOCK ( reso. 4nsec ):   
                       #   15 is close to peak: KEK-No.15  
      DelayHold:    -1 # 25MHz : internally fixed since its not useful @ 20/03/01  
      DelayL1Trig:  -1 # 6MHz  : internally fixed since its not useful @ 20/03/01  
      InExTrigger: 2   # 2: selectable internal trigger 3: external trigger (put NIM to [sync in])    
      Width: raw  

-. New important commands are as follows.

   - statusInputDAC : <ch(0..63) / all(64)> put a status file under status/ 
   - checkHVstability : check HV stability for ~ 30 min using above command  
   - setThresholdDAC   

   - setSelectbaleLogic :  <0..63> only is activated = OneCh_XX  
   - activateIndividual64 : loop using above to see trigger bevaviour on an oscilloscope        

  HV Controlles    
   - setHV       <bias voltage (00.00~90.00)> @ don't use! this increases at once @  
   - stepSetHV   <bias voltage> : step by step  
   - convergeHV  <bias voltage> : step by step and coverge it by looking HV monitor  
   - statusHV  
   - checkHV     <voltage_limit=80> <current_limit=20> <repeat_count=3>  
   - turnOffHV   : step by step to 0   
 
  Internal Trigger Ptn and Delay: see yaml/RegisterValue.yml   
   - setTriggerMode   : <0: ,>  
   - setTriggerDelay  : <0: ,>  

  Pulse Calibration:  
   - setTestPulsePtn  : <0,1,2>   
   - setTestPulseTo   : <0..63> each chip and ch by ch (recommended)   
   - calibrateIndividual64 : input test pulse to each chip and ch by ch (recommended) 
   - calibrateTrigDelayTime : scan trigger delay