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Pull requests: UCSBarchlab/PyRTL
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Added Module name change functionality for Issue #420
#427
opened Sep 27, 2022 by
spencercheese
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Implement a language agnostic hardware representation
#404
opened Sep 21, 2021 by
RhysGretsch81
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Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
#398
opened Jul 9, 2021 by
mdko
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