This repository contains Verilog projects and modules developed using Xilinx Vivado. The projects range from simple designs to more complex systems, showcasing a variety of digital design concepts. Each project is documented with relevant code, simulation results, and implementation details to provide a comprehensive understanding of the design process. Whether you're exploring state machines, traffic light controllers, or other digital logic circuits, this repository is a resource for learning and reference.
The version of Vivado used for this repository is 2024.1