target: arm: Add updates to CBAR

Support CBAR for aarch32. Signed-off-by: Sai Pavan Boddu <[email protected]> Signed-off-by: Edgar E. Iglesias <[email protected]>
Xilinx · Sep 15, 2022 · 74d70f8 · 74d70f8
1 parent b15d8d6
commit 74d70f8
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Showing 2 changed files with 23 additions and 12 deletions.
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
@@ -808,6 +808,7 @@ static void cortex_r52_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_PMSA);
     set_feature(&cpu->env, ARM_FEATURE_PMU);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     cpu->pmsav7_dregion = 16;
     cpu->midr = 0x411fd132; /* r1p2 */
     cpu->isar.id_pfr0 = 0x0131;

diff --git a/target/arm/helper.c b/target/arm/helper.c
@@ -8644,19 +8644,29 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
             define_arm_cp_regs(cpu, cbar_reginfo);
         } else {
-            ARMCPRegInfo cbar = {
-                .name = "CBAR",
-                .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
-                .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
-                .fieldoffset = offsetof(CPUARMState,
-                                        cp15.c15_config_base_address)
-            };
-            if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
-                cbar.access = PL1_R;
-                cbar.fieldoffset = 0;
-                cbar.type = ARM_CP_CONST;
+            if (arm_feature(env, ARM_FEATURE_V8)) {
+                ARMCPRegInfo cbar = {
+                    .name = "CBAR",
+                    .type = ARM_CP_CONST,
+                    .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0,
+                    .access = PL1_R | PL2_R, .resetvalue = cpu->reset_cbar
+                };
+                define_one_arm_cp_reg(cpu, &cbar);
+            } else {
+                ARMCPRegInfo cbar = {
+                    .name = "CBAR",
+                    .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
+                    .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
+                    .fieldoffset = offsetof(CPUARMState,
+                                            cp15.c15_config_base_address)
+                };
+                if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
+                    cbar.access = PL1_R;
+                    cbar.fieldoffset = 0;
+                    cbar.type = ARM_CP_CONST;
+                }
+                define_one_arm_cp_reg(cpu, &cbar);
             }
-            define_one_arm_cp_reg(cpu, &cbar);
         }
     }