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merge FX to main (fvdhoef#21)
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* refactored video modulator to use 1 less DSP and lessening the timing pressure for inputs of y_s, i_s and q_s flip flops

* added module for a pair of 8x8 unsigned multipliers

* rename of wires to make it more clear and explicit

* small cleanup

* small cleanup

* changed version number to v0.1.2

* Gave negated signals a suffix to indicate they contain the negated value of their intended value

* LUT usage reduction by refactoring and reordering

* moved address and data related logic to separate addr_data module

* LUT usage reduction by refactoring and reordering (fvdhoef#5)

* Revert: Increase audio mixing resolution (fvdhoef#7)

Co-authored-by: Natt Akuma <[email protected]>

* FX: Separate address and data logic into module (fvdhoef#8)

* LUT usage reduction by refactoring and reordering

* moved address and data related logic to separate addr_data module

* replaced another two multiplications with adders

* replaced address logic structure with extendable one, added (dummy) addr1-mode

* FX extendable structure for address logic (fvdhoef#9)

* LUT usage reduction by refactoring and reordering

* moved address and data related logic to separate addr_data module

* replaced another two multiplications with adders

* replaced address logic structure with extendable one, added (dummy) addr1-mode

* added 8bpp line draw mode

* replaced tabs by spaces

* changed naming and added comments

* [FX] Line draw mode (8bpp) (fvdhoef#10)

* LUT usage reduction by refactoring and reordering

* moved address and data related logic to separate addr_data module

* replaced another two multiplications with adders

* replaced address logic structure with extendable one, added (dummy) addr1-mode

* added 8bpp line draw mode

* replaced tabs by spaces

* changed naming and added comments

* added polygon filler helper (8bpp)

* typo and more explicit check if ADDR0/1 is untouched

* [FX] Polygon filler mode (8bpp) (fvdhoef#12)

* LUT usage reduction by refactoring and reordering

* moved address and data related logic to separate addr_data module

* replaced another two multiplications with adders

* replaced address logic structure with extendable one, added (dummy) addr1-mode

* added 8bpp line draw mode

* replaced tabs by spaces

* changed naming and added comments

* added polygon filler helper (8bpp)

* typo and more explicit check if ADDR0/1 is untouched

* added affine mode (8bpp)

* added 32-bit cache and multiplier/accumulator, including transparent writes and 16bit hop mode

* added 4-bit and 2-bit modes

* Bump version (fvdhoef#17)

* Bump version

* Set version to 0.3.1

---------

Co-authored-by: Jeffrey <[email protected]>
Co-authored-by: Joe Burks <[email protected]>
Co-authored-by: Natt Akuma <[email protected]>
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@mooinglemur @visual-trials
@jburks @akumanatt
4 people authored Oct 18, 2023
1 parent b1ada29 commit 83a9fa6
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Showing 11 changed files with 1,752 additions and 409 deletions.
1,130 changes: 1,130 additions & 0 deletions fpga/source/addr_data.v
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3 changes: 2 additions & 1 deletion fpga/source/audio/pcm.v
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,8 @@ module pcm(

// Audio output
output wire [15:0] left_audio,
output wire [15:0] right_audio);
output wire [15:0] right_audio) /* synthesis syn_hier = "hard" */;


//////////////////////////////////////////////////////////////////////////
// Audio FIFO
Expand Down
3 changes: 2 additions & 1 deletion fpga/source/audio/psg.v
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,8 @@ module psg(

// Audio output
output wire [15:0] left_audio,
output wire [15:0] right_audio);
output wire [15:0] right_audio) /* synthesis syn_hier = "hard" */;


//////////////////////////////////////////////////////////////////////////
// Audio attribute RAM
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68 changes: 46 additions & 22 deletions fpga/source/main_ram.v
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Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,9 @@ module main_ram(
// Slave bus interface
input wire [14:0] bus_addr,
input wire [31:0] bus_wrdata,
input wire [3:0] bus_wrbytesel,
input wire [7:0] bus_wrnibblesel,
output reg [31:0] bus_rddata,
input wire bus_write);
input wire bus_write) /* synthesis syn_hier = "hard" */;

wire blk10_cs = !bus_addr[14];
wire blk32_cs = bus_addr[14];
Expand All @@ -32,31 +32,55 @@ module main_ram(

always @(posedge clk) begin
if (bus_write && blk10_cs) begin
if (bus_wrbytesel[0]) begin
blk10[bus_addr][7:0] = bus_wrdata[7:0];
if (bus_wrnibblesel[0]) begin
blk10[bus_addr][3:0] = bus_wrdata[3:0];
end
if (bus_wrbytesel[1]) begin
blk10[bus_addr][15:8] = bus_wrdata[15:8];
if (bus_wrnibblesel[1]) begin
blk10[bus_addr][7:4] = bus_wrdata[7:4];
end
if (bus_wrbytesel[2]) begin
blk10[bus_addr][23:16] = bus_wrdata[23:16];
if (bus_wrnibblesel[2]) begin
blk10[bus_addr][11:8] = bus_wrdata[11:8];
end
if (bus_wrbytesel[3]) begin
blk10[bus_addr][31:24] = bus_wrdata[31:24];
if (bus_wrnibblesel[3]) begin
blk10[bus_addr][15:12] = bus_wrdata[15:12];
end
if (bus_wrnibblesel[4]) begin
blk10[bus_addr][19:16] = bus_wrdata[19:16];
end
if (bus_wrnibblesel[5]) begin
blk10[bus_addr][23:20] = bus_wrdata[23:20];
end
if (bus_wrnibblesel[6]) begin
blk10[bus_addr][27:24] = bus_wrdata[27:24];
end
if (bus_wrnibblesel[7]) begin
blk10[bus_addr][31:28] = bus_wrdata[31:28];
end
end
if (bus_write && blk32_cs) begin
if (bus_wrbytesel[0]) begin
blk32[bus_addr][7:0] = bus_wrdata[7:0];
if (bus_wrnibblesel[0]) begin
blk32[bus_addr][3:0] = bus_wrdata[3:0];
end
if (bus_wrnibblesel[1]) begin
blk32[bus_addr][7:4] = bus_wrdata[7:4];
end
if (bus_wrnibblesel[2]) begin
blk32[bus_addr][11:8] = bus_wrdata[11:8];
end
if (bus_wrnibblesel[3]) begin
blk32[bus_addr][15:12] = bus_wrdata[15:12];
end
if (bus_wrnibblesel[4]) begin
blk32[bus_addr][19:16] = bus_wrdata[19:16];
end
if (bus_wrbytesel[1]) begin
blk32[bus_addr][15:8] = bus_wrdata[15:8];
if (bus_wrnibblesel[5]) begin
blk32[bus_addr][23:20] = bus_wrdata[23:20];
end
if (bus_wrbytesel[2]) begin
blk32[bus_addr][23:16] = bus_wrdata[23:16];
if (bus_wrnibblesel[6]) begin
blk32[bus_addr][27:24] = bus_wrdata[27:24];
end
if (bus_wrbytesel[3]) begin
blk32[bus_addr][31:24] = bus_wrdata[31:24];
if (bus_wrnibblesel[7]) begin
blk32[bus_addr][31:28] = bus_wrdata[31:28];
end
end

Expand Down Expand Up @@ -86,7 +110,7 @@ module main_ram(
.AD(bus_addr[13:0]),
.DI(bus_wrdata[15:0]),
.DO(blk10_rddata[15:0]),
.MASKWE({{2{bus_wrbytesel[1]}}, {2{bus_wrbytesel[0]}}}),
.MASKWE(bus_wrnibblesel[3:0]),
.WE(bus_write && blk10_cs),
.CS(1'b1),
.STDBY(1'b0),
Expand All @@ -98,7 +122,7 @@ module main_ram(
.AD(bus_addr[13:0]),
.DI(bus_wrdata[31:16]),
.DO(blk10_rddata[31:16]),
.MASKWE({{2{bus_wrbytesel[3]}}, {2{bus_wrbytesel[2]}}}),
.MASKWE(bus_wrnibblesel[7:4]),
.WE(bus_write && blk10_cs),
.CS(1'b1),
.STDBY(1'b0),
Expand All @@ -110,7 +134,7 @@ module main_ram(
.AD(bus_addr[13:0]),
.DI(bus_wrdata[15:0]),
.DO(blk32_rddata[15:0]),
.MASKWE({{2{bus_wrbytesel[1]}}, {2{bus_wrbytesel[0]}}}),
.MASKWE(bus_wrnibblesel[3:0]),
.WE(bus_write && blk32_cs),
.CS(1'b1),
.STDBY(1'b0),
Expand All @@ -122,7 +146,7 @@ module main_ram(
.AD(bus_addr[13:0]),
.DI(bus_wrdata[31:16]),
.DO(blk32_rddata[31:16]),
.MASKWE({{2{bus_wrbytesel[3]}}, {2{bus_wrbytesel[2]}}}),
.MASKWE(bus_wrnibblesel[7:4]),
.WE(bus_write && blk32_cs),
.CS(1'b1),
.STDBY(1'b0),
Expand Down
57 changes: 57 additions & 0 deletions fpga/source/mult_accum.v
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Original file line number Diff line number Diff line change
@@ -0,0 +1,57 @@
//`default_nettype none

module mult_accum (
input wire clk,

input wire [15:0] input_a_16,
input wire [15:0] input_b_16,
input wire mult_enabled,
input wire reset_accum,
input wire accumulate,
input wire add_or_sub,

output wire [31:0] output_32);

pmi_dsp i_mult16x16 ( // port interfaces
.A(input_a_16),
.B(input_b_16),
.C(input_b_16), // This is used to pass through the original value of the cache
.D(input_a_16), // This is used to pass through the original value of the cache
.O(output_32),
.CLK(clk),
.CE(1'b1),
.IRSTTOP(1'b0),
.IRSTBOT(1'b0),
.ORSTTOP(reset_accum),
.ORSTBOT(reset_accum),
.AHOLD(1'b0),
.BHOLD(1'b0),
.CHOLD(1'b0),
.DHOLD(1'b0),
.OHOLDTOP(!accumulate),
.OHOLDBOT(!accumulate),
.OLOADTOP(!mult_enabled), // We are using the LOAD to switch between the multiplier output and (effectively) input C
.OLOADBOT(!mult_enabled), // We are using the LOAD to switch between the multiplier output and (effectively) input D
.ADDSUBTOP(add_or_sub),
.ADDSUBBOT(add_or_sub),
.CO(),
.CI(1'b0),
.ACCUMCI(1'b0),
.ACCUMCO(),
.SIGNEXTIN(1'b0),
.SIGNEXTOUT()
);
defparam i_mult16x16.TOPOUTPUT_SELECT = 2'b00; // Adder output (non registered)
defparam i_mult16x16.BOTOUTPUT_SELECT = 2'b00; // Adder output (non registered)
defparam i_mult16x16.A_SIGNED = 1'b1; //Signed Inputs
defparam i_mult16x16.B_SIGNED = 1'b1;

defparam i_mult16x16.TOPADDSUB_CARRYSELECT = 2'b10; // 10: Cascade ACCUMOUT from lower Adder/Subtractor

defparam i_mult16x16.TOPADDSUB_LOWERINPUT = 2'b10; // We send the output (the 16 upper bits) of the 16x16 multiplier to the lower side of the top accumilator
defparam i_mult16x16.TOPADDSUB_UPPERINPUT = 1'b0; // We send the output of the top (output) flip-flop to the upper side of the top accumilator
defparam i_mult16x16.BOTADDSUB_LOWERINPUT = 2'b10; // We send the output (the 16 lower bits) of the 16x16 multiplier to the lower side of the bottom accumilator
defparam i_mult16x16.BOTADDSUB_UPPERINPUT = 1'b0; // We send the output of the bottom (output) flip-flop to the upper side of the top accumilator


endmodule
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