FIX: The open export page fix for unit tests (#5363)

Co-authored-by: Sébastien Morais <[email protected]>

src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py

@@ -1310,7 +1310,7 @@ def substrate_resistivity(self, substrate_input):
         ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status)
 
     @property
-    def substrate_loss_tangent(self) -> Union[SubstrateType, str]:
+    def substrate_loss_tangent(self) -> Union[SubstrateEr, str]:
         """Substrate's loss tangent.
         The value can be either a string or an instance of the ``SubstrateEr`` enum.
         The default is ``0.0005`` for ``SubstrateEr.ALUMINA``.

tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg

@@ -1,31 +1,31 @@
 modsubType=2
-modsubEr=4.5
-modsubRho=5.8E+07
-modsubTand=0.035
-modsubH=0.002
-modsubT=5E-07
+modsubEr=9.8
+modsubRho=1.43
+modsubTand=0.0005
+modsubH=0.00127
+modsubT=2.54E-06
 modsubS=0.00127
 modsubC=0.00635
-modsubErsel=-1
-modsubRhosel=-1
-modsubTandsel=-1
-modsubTanddef=0
+modsubErsel=1
+modsubRhosel=3
+modsubTandsel=1
+modsubTanddef=1
 modsubiSubSel=0
-modsubName=User Defined Substrate
+modsubName=Alumina
 modsubBrow=
-modsubNameVal=4.5
+modsubNameVal=Alumina:             9.8
 modAnsSubIndex=0
 modAWRSubIndex=0
 webAWRSubIndex=0
 locAWRSubIndex=0
-ModelData=2
+ModelData=0
 ModelDataV=1
 ModelInd=0
-ModelCap=3
+ModelCap=0
 ModelRes=0
-ModelIndV=1
-ModelCapV=1
-ModelResV=1
+ModelIndV=0
+ModelCapV=0
+ModelResV=0
 modRatLen=2
 modRatZ=1
 Interc=1