Add name

ansys · Nov 12, 2024 · 7b6795a · 7b6795a
1 parent 3961a46
commit 7b6795a
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/tests/system/general/test_21_Circuit.py b/tests/system/general/test_21_Circuit.py
@@ -517,7 +517,7 @@ def test_35_netlist_data_block(self):
         assert self.aedtapp.analyze()
 
     def test_36_create_voltage_probe(self):
-        myprobe = self.aedtapp.modeler.components.create_voltage_probe()
+        myprobe = self.aedtapp.modeler.components.create_voltage_probe(name="voltage_probe")
         assert type(myprobe.id) is int
 
     def test_37_draw_graphical_primitives(self):