test #68 done

ansys · Oct 24, 2024 · 4595b24 · 4595b24
1 parent c1b4261
commit 4595b24
Showing 1 changed file with 6 additions and 10 deletions.
diff --git a/tests/grpc/system/test_edb_modeler.py b/tests/grpc/system/test_edb_modeler.py
@@ -524,17 +524,13 @@ def test_layer_name(self, edb_examples):
         assert edbapp.modeler.polygons[50].layer_name == "16_Bottom"
         edbapp.close()
 
-    def test_287_circuit_ports(self):
-        example_folder = os.path.join(local_path, "example_models", test_subfolder)
-        source_path_edb = os.path.join(example_folder, "ANSYS-HSD_V1.aedb")
-        target_path_edb = os.path.join(self.local_scratch.path, "test_create_polygon", "test.aedb")
-        self.local_scratch.copyfolder(source_path_edb, target_path_edb)
-        edbapp = Edb(target_path_edb, desktop_version)
+    def test_287_circuit_ports(self, edb_examples):
+        # Done
+        edbapp = edb_examples.get_si_verse()
         cap = edbapp.components.capacitors["C1"]
-        edbapp.siwave.create_circuit_port_on_pin(pos_pin=cap.pins["1"]._edb_object, neg_pin=cap.pins["2"]._edb_object)
-        edbapp.save_edb_as(r"C:\Users\gkorompi\Downloads\AFT")
-        edbapp.components.capacitors["C3"].pins
-        edbapp.padstacks.pins
+        assert edbapp.siwave.create_circuit_port_on_pin(pos_pin=cap.pins["1"], neg_pin=cap.pins["2"])
+        assert edbapp.components.capacitors["C3"].pins
+        assert edbapp.padstacks.pins
         edbapp.close()
 
     def rlc_component_302(self):