Fix documentation build

doc/Makefile

@@ -26,7 +26,7 @@ clean:
 
 # build html docs in parallel using all available CPUs
 # WARNING: this is a resource hog
-phtml:
+html:
 	$(SPHINXBUILD) -M html "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) -j auto
 
 # Build pdf docs.

doc/source/User_guide/Edb_information_queries/get_layout_bounding_box.rst

@@ -17,6 +17,6 @@ This section describes how to retrieve the layout size by getting the bounding b
 
     edbapp.get_bounding_box()
 
-.. image:: ../../Resources/layout_bbox.png
-    :width: 800
-    :alt: Layout bounding box
+.. .. image:: ../../Resources/layout_bbox.png
+..     :width: 800
+..     :alt: Layout bounding box

doc/source/User_guide/Excitations/create_coax_port_on_component.rst

@@ -26,6 +26,6 @@ This section shows a simple example to create HFSS coaxial port on a component.
 
 - In this example coaxial port on Nets DDR4_DSQ0_P and DDR4_DSQ0_N from componennt U1 are created.
 
-.. image:: ../../Resources/create_port_on_component_simple.png
-  :width: 800
-  :alt: Create port on component
+.. .. image:: ../../Resources/create_port_on_component_simple.png
+..   :width: 800
+..   :alt: Create port on component

doc/source/conf.py

@@ -323,10 +323,10 @@ def setup(app):
             "icon": "fa fa-comment fa-fw",
         },
     ],
-    "switcher": {
-        "json_url": f"https://{cname}/versions.json",
-        "version_match": get_version_match(__version__),
-    },
+    # "switcher": {
+    #     "json_url": f"https://{cname}/versions.json",
+    #     "version_match": get_version_match(__version__),
+    # },
     "collapse_navigation": True,
     "use_meilisearch": {
         "api_key": os.getenv("MEILISEARCH_PUBLIC_API_KEY", ""),

src/pyedb/generic/design_types.py

@@ -19,7 +19,7 @@ def Edb(
 
     Parameters
     ----------
-    edbpath : str, int, float optional
+    edbpath : str, optional
         Full path to the ``aedb`` folder. The variable can also contain
         the path to a layout to import. Allowed formats are BRD,
         XML (IPC2581), GDS, and DXF. The default is ``None``.

src/pyedb/legacy/edb.py

@@ -102,7 +102,7 @@ class EdbLegacy(Database):
         owned by HFSS 3D Layout. The default is ``False``.
     edbversion : str, int, float, optional
         Version of EDB to use. The default is ``None``.
-        Examples of input values are ``232``, ``23.2``,``2023.2``,``"2023.2"``.
+        Examples of input values are ``232``, ``23.2``, ``2023.2``, ``"2023.2"``.
     isaedtowned : bool, optional
         Whether to launch EDB from HFSS 3D Layout. The
         default is ``False``.
@@ -111,7 +111,8 @@ class EdbLegacy(Database):
     student_version : bool, optional
         Whether to open the AEDT student version. The default is ``False.``
     technology_file : str, optional
-        Full path to technology file to be converted to xml before importing or xml. Supported by GDS format only.
+        Full path to technology file to be converted to xml before importing or xml.
+        Supported by GDS format only.
 
     Examples
     --------
@@ -136,7 +137,6 @@ class EdbLegacy(Database):
     >>> app['s2'].description
     >>> 'Spacing between traces'
 
-
     Create an ``Edb`` object and open the specified project.
 
     >>> app = EdbLegacy("myfile.aedb")
@@ -3935,15 +3935,15 @@ def create_voltage_source(self, terminal, ref_terminal):
 
         Parameters
         ----------
-        terminal : :class:`pyedb.legacy.edb_core.edb_data.terminals.EdgeTerminal`,
-                   :class:`pyedb.legacy.edb_core.edb_data.terminals.PadstackInstanceTerminal`,
-                   :class:`pyedb.legacy.edb_core.edb_data.terminals.PointTerminal`,
-                   :class:`pyedb.legacy.edb_core.edb_data.terminals.PinGroupTerminal`,
+        terminal : :class:`pyedb.legacy.edb_core.edb_data.terminals.EdgeTerminal`, \
+            :class:`pyedb.legacy.edb_core.edb_data.terminals.PadstackInstanceTerminal`, \
+            :class:`pyedb.legacy.edb_core.edb_data.terminals.PointTerminal`, \
+            :class:`pyedb.legacy.edb_core.edb_data.terminals.PinGroupTerminal`
             Positive terminal of the port.
-        ref_terminal : class:`pyedb.legacy.edb_core.edb_data.terminals.EdgeTerminal`,
-                   :class:`pyedb.legacy.edb_core.edb_data.terminals.PadstackInstanceTerminal`,
-                   :class:`pyedb.legacy.edb_core.edb_data.terminals.PointTerminal`,
-                   :class:`pyedb.legacy.edb_core.edb_data.terminals.PinGroupTerminal`,
+        ref_terminal : class:`pyedb.legacy.edb_core.edb_data.terminals.EdgeTerminal`, \
+            :class:`pyedb.legacy.edb_core.edb_data.terminals.PadstackInstanceTerminal`, \
+            :class:`pyedb.legacy.edb_core.edb_data.terminals.PointTerminal`, \
+            :class:`pyedb.legacy.edb_core.edb_data.terminals.PinGroupTerminal`
             Negative terminal of the source.
 
         Returns
@@ -4028,29 +4028,30 @@ def auto_parametrize_design(
         trace_net_filter=None,
     ):
         """Assign automatically design and project variables with current values.
+
         Parameters
         ----------
         layers : bool, optional
-                 ``True`` enable layer thickness parametrization. Default value is ``True``.
+            Enable layer thickness parametrization. Default value is ``True``.
         materials : bool, optional
-                 ``True`` enable material parametrization. Default value is ``True``.
+            Enable material parametrization. Default value is ``True``.
         via_holes : bool, optional
-                 ``True`` enable via diameter parametrization. Default value is ``True``.
+            Enable via diameter parametrization. Default value is ``True``.
         pads : bool, optional
-                 ``True`` enable pads size parametrization. Default value is ``True``.
+            Enable pads size parametrization. Default value is ``True``.
         antipads : bool, optional
-                 ``True`` enable anti pads size parametrization. Default value is ``True``.
+            Enable anti pads size parametrization. Default value is ``True``.
         traces : bool, optional
-                 ``True`` enable trace width parametrization. Default value is ``True``.
+            Enable trace width parametrization. Default value is ``True``.
         layer_filter : str, List(str), optional
-                 Enable layer filter. Default value is ``None``, all layers are parametrized.
+            Enable layer filter. Default value is ``None``, all layers are parametrized.
         material_filter : str, List(str), optional
-                 Enable material filter. Default value is ``None``, all material are parametrized.
+            Enable material filter. Default value is ``None``, all material are parametrized.
         padstack_definition_filter : str, List(str), optional
-                 Enable padstack definition filter. Default value is ``None``, all padsatcks are parametrized.
+            Enable padstack definition filter. Default value is ``None``, all padsatcks are parametrized.
         trace_net_filter : str, List(str), optional
-                 Enable nets filter for trace width parametrization. Default value is ``None``, all layers are
-                 parametrized.
+            Enable nets filter for trace width parametrization. Default value is ``None``, all layers are parametrized.
+
         Returns
         -------
         List(str)

src/pyedb/legacy/edb_core/edb_data/padstacks_data.py

@@ -1145,9 +1145,9 @@ def create_port(self, name=None, reference=None, is_circuit_port=False):
         ----------
         name : str, optional
             Name of the port. The default is ``None``, in which case a name is automatically assigned.
-        reference : class:`pyedb.legacy.edb_core.edb_data.nets_data.EDBNetsData`,
-                    class:`pyedb.legacy.edb_core.edb_data.padstacks_data.EDBPadstackInstance`,
-                    class:`pyedb.legacy.edb_core.edb_data.sources.PinGroup`, optional
+        reference : class:`pyedb.legacy.edb_core.edb_data.nets_data.EDBNetsData`, \
+            class:`pyedb.legacy.edb_core.edb_data.padstacks_data.EDBPadstackInstance`, \
+            class:`pyedb.legacy.edb_core.edb_data.sources.PinGroup`, optional
             Negative terminal of the port.
         is_circuit_port : bool, optional
             Whether it is a circuit port.

src/pyedb/legacy/edb_core/edb_data/simulation_setup.py

@@ -226,6 +226,7 @@ def add_frequency_sweep(self, name=None, frequency_sweep=None):
 
 class EdbFrequencySweep(object):
     """Manages EDB methods for a frequency sweep.
+
     Parameters
     ----------
     sim_setup : :class:`pyedb.legacy.edb_core.edb_data.siwave_simulation_setup_data.SiwaveSYZSimulationSetup`

src/pyedb/legacy/edb_core/edb_data/siwave_simulation_setup_data.py

@@ -1095,6 +1095,7 @@ def use_si_settings(self, value):
 
 class SiwaveDCSimulationSetup(SiwaveSYZSimulationSetup):
     """Manages EDB methods for SIwave DC simulation setup.
+
     Parameters
     ----------
     pedb : :class:`pyedb.legacy.edb.Edb`