page_table: change the name of a variable for clarity

arceos-hypervisor · Jul 31, 2024 · 3a38f85 · 3a38f85
1 parent 09e4c21
commit 3a38f85
Showing 1 changed file with 5 additions and 5 deletions.
diff --git a/page_table_multiarch/src/bits64.rs b/page_table_multiarch/src/bits64.rs
@@ -427,29 +427,29 @@ impl<M: PagingMetaData, PTE: GenericPTE, H: PagingHandler> PageTable64<M, PTE, H
     }
 
     fn get_entry_mut(&mut self, vaddr: M::VirtAddr) -> PagingResult<(&mut PTE, PageSize)> {
-        let vaddr_usize: usize = vaddr.into();
+        let vaddr: usize = vaddr.into();
         let p3 = if M::LEVELS == 3 {
             self.table_of_mut(self.root_paddr())
         } else if M::LEVELS == 4 {
             let p4 = self.table_of_mut(self.root_paddr());
-            let p4e = &mut p4[p4_index(vaddr_usize)];
+            let p4e = &mut p4[p4_index(vaddr)];
             self.next_table_mut(p4e)?
         } else {
             unreachable!()
         };
-        let p3e = &mut p3[p3_index(vaddr_usize)];
+        let p3e = &mut p3[p3_index(vaddr)];
         if p3e.is_huge() {
             return Ok((p3e, PageSize::Size1G));
         }
 
         let p2 = self.next_table_mut(p3e)?;
-        let p2e = &mut p2[p2_index(vaddr_usize)];
+        let p2e = &mut p2[p2_index(vaddr)];
         if p2e.is_huge() {
             return Ok((p2e, PageSize::Size2M));
         }
 
         let p1 = self.next_table_mut(p2e)?;
-        let p1e = &mut p1[p1_index(vaddr_usize)];
+        let p1e = &mut p1[p1_index(vaddr)];
         Ok((p1e, PageSize::Size4K))
     }