Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

riscv vcpu implemention #2

Open
wants to merge 12 commits into
base: master
Choose a base branch
from
Open

riscv vcpu implemention #2

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
12 commits
Select commit Hold shift + click to select a range
a1a3a61
WIP: remove csr
PeizhongQiu Sep 1, 2024
8a495b9
enable irq
PeizhongQiu Sep 1, 2024
39322c0
disable irq
PeizhongQiu Sep 2, 2024
606c92b
modify readme
PeizhongQiu Sep 2, 2024
f886875
disable irq
PeizhongQiu Sep 2, 2024
7b642d9
fmt
PeizhongQiu Sep 2, 2024
9b294f0
fmt
PeizhongQiu Sep 2, 2024
fe74819
add set_gpr
PeizhongQiu Sep 2, 2024
4dd9ace
modify set_gpr
PeizhongQiu Sep 4, 2024
6010c50
modify ci
PeizhongQiu Sep 4, 2024
a924e42
doc
PeizhongQiu Sep 4, 2024
28408aa
test ci
PeizhongQiu Sep 4, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 3 additions & 3 deletions src/regs.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -93,12 +93,12 @@ impl GeneralPurposeRegisters {
}

/// Sets the value of the given register.
pub fn set_reg(&mut self, reg_index: GprIndex, val: usize) {
if reg_index == GprIndex::Zero {
pub fn set_reg(&mut self, reg_index: usize, val: usize) {
PeizhongQiu marked this conversation as resolved.
Show resolved Hide resolved
if reg_index == 0 {
return;
}

self.0[reg_index as usize] = val;
self.0[reg_index] = val;
}

/// Returns the argument registers.
Expand Down
64 changes: 36 additions & 28 deletions src/vcpu.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@ use crate::timers::register_timer;
use crate::timers::TimerEventFn;
use axaddrspace::{GuestPhysAddr, HostPhysAddr, MappingFlags};
use axerrno::AxResult;
use axvcpu::AxArchVCpu;
PeizhongQiu marked this conversation as resolved.
Show resolved Hide resolved
use axvcpu::AxVCpuExitReason;
use core::mem::size_of;
use riscv::addr::BitField;
Expand All @@ -26,7 +27,7 @@ pub struct RISCVVCpu {
regs: VmCpuRegisters,
}

impl axvcpu::AxArchVCpu for RISCVVCpu {
impl AxArchVCpu for RISCVVCpu {
type CreateConfig = ();

type SetupConfig = ();
Expand All @@ -48,9 +49,11 @@ impl axvcpu::AxArchVCpu for RISCVVCpu {
sstatus.set_spp(sstatus::SPP::Supervisor);
regs.guest_regs.sstatus = sstatus.bits();

regs.guest_regs.gprs.set_reg(GprIndex::A0, 0);
regs.guest_regs.gprs.set_reg(GprIndex::A0 as usize, 0);
// TODO:from _config
regs.guest_regs.gprs.set_reg(GprIndex::A1, 0x9000_0000);
regs.guest_regs
.gprs
.set_reg(GprIndex::A1 as usize, 0x9000_0000);

Ok(Self { regs })
}
Expand Down Expand Up @@ -96,6 +99,11 @@ impl axvcpu::AxArchVCpu for RISCVVCpu {
// unimplemented!()
Ok(())
}

/// Set one of the vCPU's general purpose register.
fn set_gpr(&mut self, index: usize, val: usize) {
self.regs.guest_regs.gprs.set_reg(index, val);
PeizhongQiu marked this conversation as resolved.
Show resolved Hide resolved
}
}

impl RISCVVCpu {
Expand All @@ -104,11 +112,6 @@ impl RISCVVCpu {
self.regs.guest_regs.gprs.reg(index)
}

/// Set one of the vCPU's general purpose register.
pub fn set_gpr(&mut self, index: GprIndex, val: usize) {
self.regs.guest_regs.gprs.set_reg(index, val);
}

/// Advance guest pc by `instr_len` bytes
pub fn advance_pc(&mut self, instr_len: usize) {
self.regs.guest_regs.sepc += instr_len
Expand Down Expand Up @@ -180,7 +183,7 @@ impl RISCVVCpu {
}
SbiMessage::GetChar => {
let c = sbi_rt::legacy::console_getchar();
self.set_gpr(GprIndex::A0, c);
self.set_gpr(GprIndex::A0 as usize, c);
}
SbiMessage::PutChar(c) => {
sbi_rt::legacy::console_putchar(c);
Expand Down Expand Up @@ -225,51 +228,54 @@ impl RISCVVCpu {
match base {
BaseFunction::GetSepcificationVersion => {
let version = sbi_rt::get_spec_version();
self.set_gpr(GprIndex::A1, version.major() << 24 | version.minor());
self.set_gpr(
GprIndex::A1 as usize,
version.major() << 24 | version.minor(),
);
debug!(
"GetSepcificationVersion: {}",
version.major() << 24 | version.minor()
);
}
BaseFunction::GetImplementationID => {
let id = sbi_rt::get_sbi_impl_id();
self.set_gpr(GprIndex::A1, id);
self.set_gpr(GprIndex::A1 as usize, id);
}
BaseFunction::GetImplementationVersion => {
let impl_version = sbi_rt::get_sbi_impl_version();
self.set_gpr(GprIndex::A1, impl_version);
self.set_gpr(GprIndex::A1 as usize, impl_version);
}
BaseFunction::ProbeSbiExtension(extension) => {
let extension = sbi_rt::probe_extension(extension as usize).raw;
self.set_gpr(GprIndex::A1, extension);
self.set_gpr(GprIndex::A1 as usize, extension);
}
BaseFunction::GetMachineVendorID => {
let mvendorid = sbi_rt::get_mvendorid();
self.set_gpr(GprIndex::A1, mvendorid);
self.set_gpr(GprIndex::A1 as usize, mvendorid);
}
BaseFunction::GetMachineArchitectureID => {
let marchid = sbi_rt::get_marchid();
self.set_gpr(GprIndex::A1, marchid);
self.set_gpr(GprIndex::A1 as usize, marchid);
}
BaseFunction::GetMachineImplementationID => {
let mimpid = sbi_rt::get_mimpid();
self.set_gpr(GprIndex::A1, mimpid);
self.set_gpr(GprIndex::A1 as usize, mimpid);
}
}
self.set_gpr(GprIndex::A0, 0);
self.set_gpr(GprIndex::A0 as usize, 0);
Ok(())
}

fn handle_rfnc_function(&mut self, rfnc: RemoteFenceFunction) -> AxResult<()> {
self.set_gpr(GprIndex::A0, 0);
self.set_gpr(GprIndex::A0 as usize, 0);
match rfnc {
RemoteFenceFunction::FenceI {
hart_mask,
hart_mask_base,
} => {
let sbi_ret = sbi_rt::remote_fence_i(hart_mask as usize, hart_mask_base as usize);
self.set_gpr(GprIndex::A0, sbi_ret.error);
self.set_gpr(GprIndex::A1, sbi_ret.value);
self.set_gpr(GprIndex::A0 as usize, sbi_ret.error);
self.set_gpr(GprIndex::A1 as usize, sbi_ret.value);
}
RemoteFenceFunction::RemoteSFenceVMA {
hart_mask,
Expand All @@ -283,21 +289,23 @@ impl RISCVVCpu {
start_addr as usize,
size as usize,
);
self.set_gpr(GprIndex::A0, sbi_ret.error);
self.set_gpr(GprIndex::A1, sbi_ret.value);
self.set_gpr(GprIndex::A0 as usize, sbi_ret.error);
self.set_gpr(GprIndex::A1 as usize, sbi_ret.value);
}
}
Ok(())
}

fn handle_pmu_function(&mut self, pmu: PmuFunction) -> AxResult<()> {
self.set_gpr(GprIndex::A0, 0);
self.set_gpr(GprIndex::A0 as usize, 0);
match pmu {
PmuFunction::GetNumCounters => self.set_gpr(GprIndex::A1, sbi_rt::pmu_num_counters()),
PmuFunction::GetNumCounters => {
self.set_gpr(GprIndex::A1 as usize, sbi_rt::pmu_num_counters())
}
PmuFunction::GetCounterInfo(counter_index) => {
let sbi_ret = pmu_counter_get_info(counter_index as usize);
self.set_gpr(GprIndex::A0, sbi_ret.error);
self.set_gpr(GprIndex::A1, sbi_ret.value);
self.set_gpr(GprIndex::A0 as usize, sbi_ret.error);
self.set_gpr(GprIndex::A1 as usize, sbi_ret.value);
}
PmuFunction::StopCounter {
counter_index,
Expand All @@ -309,8 +317,8 @@ impl RISCVVCpu {
counter_mask as usize,
stop_flags as usize,
);
self.set_gpr(GprIndex::A0, sbi_ret.error);
self.set_gpr(GprIndex::A1, sbi_ret.value);
self.set_gpr(GprIndex::A0 as usize, sbi_ret.error);
self.set_gpr(GprIndex::A1 as usize, sbi_ret.value);
PeizhongQiu marked this conversation as resolved.
Show resolved Hide resolved
}
}
Ok(())
Expand Down
Loading