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28 changes: 0 additions & 28 deletions
28
.../Multi/Applications/LoRa/AT_Slave/SW4STM32/B-L072Z-LRWAN1/mlm32l07x01/mlm32l07x01 Run.cfg
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# This is an B-L072Z-LRWAN1 board with a single STM32L072CZYx chip | ||
# | ||
# Generated by System Workbench for STM32 | ||
# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s) | ||
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source [find interface/stlink.cfg] | ||
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set WORKAREASIZE 0x5000 | ||
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transport select "hla_swd" | ||
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set CHIPNAME STM32L072CZYx | ||
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# Enable debug when in low power modes | ||
set ENABLE_LOW_POWER 1 | ||
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# Stop Watchdog counters when halt | ||
set STOP_WATCHDOG 1 | ||
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# STlink Debug clock frequency | ||
set CLOCK_FREQ 4000 | ||
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# use hardware reset, connect under reset | ||
# connect_assert_srst needed if low power mode application running (WFI...) | ||
reset_config srst_only srst_nogate connect_assert_srst | ||
set CONNECT_UNDER_RESET 1 | ||
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source [find target/stm32l0x.cfg] | ||
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