feat(AXISTREAM): Add AXISTREAM peripherals and tests;

- Remove unused `tester_top_system` folder. This resolves issue IObundle#27.
arturum1 · Jun 20, 2023 · 5aeb194 · 5aeb194
1 parent db23e0f
commit 5aeb194
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Showing 10 changed files with 396 additions and 1,491 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -13,3 +13,6 @@
 [submodule "submodules/GPIO"]
 	path = submodules/GPIO
 	url = [email protected]:IObundle/iob-gpio.git
+[submodule "submodules/AXISTREAM"]
+	path = submodules/AXISTREAM
+	url = [email protected]:IObundle/iob-axis.git
diff --git a/iob_soc_sut.py b/iob_soc_sut.py
@@ -6,6 +6,8 @@
 from iob_regfileif import iob_regfileif
 from iob_gpio import iob_gpio
 from iob_eth import iob_eth
+from iob_axistream_in import iob_axistream_in
+from iob_axistream_out import iob_axistream_out
 
 sut_regs = [
     {
@@ -80,13 +82,29 @@ def _run_setup(cls):
         iob_regfileif_custom.setup()
         iob_gpio.setup()
         # iob_eth.setup()
+        iob_axistream_in.setup()
+        iob_axistream_out.setup()
 
         # Instantiate SUT peripherals
         cls.peripherals.append(
             iob_regfileif_custom.instance("REGFILEIF0", "Register file interface")
         )
         cls.peripherals.append(iob_gpio.instance("GPIO0", "GPIO interface"))
         # cls.peripherals.append(iob_eth.instance("ETH0", "Ethernet interface"))
+        cls.peripherals.append(
+            iob_axistream_in.instance(
+                "AXISTREAMIN0",
+                "SUT AXI input stream interface",
+                parameters={"TDATA_W": "32"},
+            )
+        )
+        cls.peripherals.append(
+            iob_axistream_out.instance(
+                "AXISTREAMOUT0",
+                "SUT AXI output stream interface",
+                parameters={"TDATA_W": "32"},
+            )
+        )
 
         cls.peripheral_portmap += [
             (  # Map REGFILEIF0 to external interface

diff --git a/software/src/iob_soc_sut_firmware.c b/software/src/iob_soc_sut_firmware.c
@@ -8,6 +8,10 @@
 #include "printf.h"
 #include "iob_regfileif_inverted_swreg.h"
 #include "iob_str.h"
+#include "iob-axistream-in.h"
+#include "iob-axistream-out.h"
+
+void axistream_loopback();
 
 int main()
 {
@@ -22,6 +26,9 @@ int main()
   IOB_REGFILEIF_INVERTED_INIT_BASEADDR(REGFILEIF0_BASE);
   //init gpio
   gpio_init(GPIO0_BASE);   
+  //init axistream
+  axistream_in_init(AXISTREAMIN0_BASE);   
+  axistream_out_init_tdata_w(AXISTREAMOUT0_BASE, 4);
 
   //Write to UART0 connected to the Tester.
   uart_puts("[SUT]: This message was sent from SUT!\n\n");
@@ -43,6 +50,9 @@ int main()
   gpio_set(0xabcd1234);
   uart_puts("[SUT]: Placed test pattern 0xabcd1234 in GPIO outputs.\n\n");
 
+  // Read AXI stream input and relay data to AXI stream output
+  axistream_loopback();
+
 #ifdef USE_EXTMEM
   char sutMemoryMessage[]="This message is stored in SUT's memory\n";
 
@@ -63,3 +73,28 @@ int main()
 
   uart_finish();
 }
+
+
+// Read AXI stream input, print, and relay data to AXI stream output
+void axistream_loopback(){
+  uint8_t byte_stream[64];
+  uint8_t i, total_received_bytes;
+
+  //Check if we are receiving an AXI stream
+  if(!axistream_in_empty()){
+    // Receive bytes while stream does not end (by TLAST signal), or up to 64 bytes
+    for(total_received_bytes=0; !axistream_in_pop(byte_stream+total_received_bytes, &i) && total_received_bytes<64;total_received_bytes+=i);
+    if(total_received_bytes<64)total_received_bytes += i;
+    // Print received bytes
+    uart_puts("[SUT]: Received AXI stream bytes: ");
+    for(i=0;i<total_received_bytes;i++)printf("%d ", byte_stream[i]);
+    // Send bytes to AXI stream output
+    for(i=0;i<total_received_bytes-1;i++)axistream_out_push(byte_stream+i,1,0);
+    axistream_out_push(byte_stream+i,1,1); // Send the last byte with the TLAST signal
+    uart_puts("\n[SUT]: Sent AXI stream bytes back via output interface.\n\n");
+  } else {
+    // Input AXI stream queue is empty
+    uart_puts("[SUT]: AXI stream input is empty. Skipping AXI stream tranfer.\n\n");
+  }
+
+}
diff --git a/submodules/AXISTREAM b/submodules/AXISTREAM
diff --git a/submodules/LIB b/submodules/LIB
diff --git a/submodules/TESTER/iob_soc_tester.py b/submodules/TESTER/iob_soc_tester.py
@@ -2,9 +2,11 @@
 import os
 
 from iob_soc import iob_soc
+from iob_soc_sut import iob_soc_sut
 from iob_gpio import iob_gpio
 from iob_uart import iob_uart
-from iob_soc_sut import iob_soc_sut
+from iob_axistream_in import iob_axistream_in
+from iob_axistream_out import iob_axistream_out
 
 
 class iob_soc_tester(iob_soc):
@@ -21,6 +23,8 @@ def _run_setup(cls):
         iob_uart.setup()
         iob_soc_sut.setup()
         iob_gpio.setup()
+        iob_axistream_in.setup()
+        iob_axistream_out.setup()
 
         # Instantiate SUT peripherals
         cls.peripherals.append(iob_uart.instance("UART1", "UART interface for communication with SUT"))
@@ -33,6 +37,8 @@ def _run_setup(cls):
                                     }))
 
         cls.peripherals.append(iob_gpio.instance("GPIO0", "GPIO interface"))
+        cls.peripherals.append(iob_axistream_in.instance("AXISTREAMIN0", "Tester AXI input stream interface", parameters={"TDATA_W": "32"}))
+        cls.peripherals.append(iob_axistream_out.instance("AXISTREAMOUT0", "Tester AXI output stream interface", parameters={"TDATA_W": "32"}))
 
         # Set name of sut firmware (used to join sut firmware with tester firmware)
         cls.sut_fw_name = "iob_soc_sut_firmware.c"
@@ -104,6 +110,121 @@ def _setup_portmap(cls):
                 },
                 {"corename": "external", "if_name": "SUT_GPIO", "port": "", "bits": []},
             ),
+            # SUT AXISTREAM IN
+            (
+                {
+                    "corename": "SUT0",
+                    "if_name": "AXISTREAMIN0",
+                    "port": "tvalid_i",
+                    "bits": [],
+                },
+                {
+                    "corename": "AXISTREAMOUT0",
+                    "if_name": "axistream",
+                    "port": "tvalid_o",
+                    "bits": [],
+                },
+            ),
+            (
+                {
+                    "corename": "SUT0",
+                    "if_name": "AXISTREAMIN0",
+                    "port": "tready_o",
+                    "bits": [],
+                },
+                {
+                    "corename": "AXISTREAMOUT0",
+                    "if_name": "axistream",
+                    "port": "tready_i",
+                    "bits": [],
+                },
+            ),
+            (
+                {
+                    "corename": "SUT0",
+                    "if_name": "AXISTREAMIN0",
+                    "port": "tdata_i",
+                    "bits": [],
+                },
+                {
+                    "corename": "AXISTREAMOUT0",
+                    "if_name": "axistream",
+                    "port": "tdata_o",
+                    "bits": [],
+                },
+            ),
+            (
+                {
+                    "corename": "SUT0",
+                    "if_name": "AXISTREAMIN0",
+                    "port": "tlast_i",
+                    "bits": [],
+                },
+                {
+                    "corename": "AXISTREAMOUT0",
+                    "if_name": "axistream",
+                    "port": "tlast_o",
+                    "bits": [],
+                },
+            ),
+            # SUT AXISTREAM OUT
+            (
+                {
+                    "corename": "SUT0",
+                    "if_name": "AXISTREAMOUT0",
+                    "port": "tvalid_o",
+                    "bits": [],
+                },
+                {
+                    "corename": "AXISTREAMIN0",
+                    "if_name": "axistream",
+                    "port": "tvalid_i",
+                    "bits": [],
+                },
+            ),
+            (
+                {
+                    "corename": "SUT0",
+                    "if_name": "AXISTREAMOUT0",
+                    "port": "tready_i",
+                    "bits": [],
+                },
+                {
+                    "corename": "AXISTREAMIN0",
+                    "if_name": "axistream",
+                    "port": "tready_o",
+                    "bits": [],
+                },
+            ),
+            (
+                {
+                    "corename": "SUT0",
+                    "if_name": "AXISTREAMOUT0",
+                    "port": "tdata_o",
+                    "bits": [],
+                },
+                {
+                    "corename": "AXISTREAMIN0",
+                    "if_name": "axistream",
+                    "port": "tdata_i",
+                    "bits": [],
+                },
+            ),
+            (
+                {
+                    "corename": "SUT0",
+                    "if_name": "AXISTREAMOUT0",
+                    "port": "tlast_o",
+                    "bits": [],
+                },
+                {
+                    "corename": "AXISTREAMIN0",
+                    "if_name": "axistream",
+                    "port": "tlast_i",
+                    "bits": [],
+                },
+            ),
+
         ]
 
     @classmethod