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Release 1.3.6
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@kristopk kristopk released this 26 Jan 00:15
· 91 commits to master since this release
v1.3.6
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Release 1.3.6 (See ERRATA for unsupported features)

  • Simulation model bug fix for transfer size of 64 bytes
  • Xilinx 2017.1 Patch AR70350 - fixes report_power hangs. Patch is automatically applied during setup scripts using MYVIVADO environment variable
  • Updated synthesis scripts with -sv option when calling read_verilog
  • Added documentation on us-gov-west-1 (GovCloud US)
  • Minor EDMA driver fixes and improvements
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