Release 1.3.6d

Errata updates

Release 1.3.6c

Release 1.3.6c (See ERRATA for unsupported features)

• Fixes for SDAccel 1DDR and IPI

Release 1.3.6

Release 1.3.6 (See ERRATA for unsupported features)

• Simulation model bug fix for transfer size of 64 bytes
• Xilinx 2017.1 Patch AR70350 - fixes report_power hangs. Patch is automatically applied during setup scripts using MYVIVADO environment variable
• Updated synthesis scripts with -sv option when calling read_verilog
• Added documentation on us-gov-west-1 (GovCloud US)
• Minor EDMA driver fixes and improvements

Release 1.3.5

Release 1.3.5 (See ERRATA for unsupported features)

• Amazon FPGA Images (AFIs) Tagging - To help with managing AFIs, you can optionally assign your own metadata to each AFI in the form of tags. Tags are managed using the AWS EC2 CLI commands create-tags, describe-tags and delete-tags. Tags are custom key/value pairs that can be used to identify or group EC2 resources, including AFIs. Tags can be used as filters in the describe-fpga-images API to search and filter the AFIs based on the tags you add.
• EDMA driver fixes and improvements, including polled DMA descriptor completion mode which improves performance on smaller IO (<1MB)
• AFI Power metrics and warnings – developers can avoid power violations by monitoring metrics that provide recent FPGA power, maximum FPGA power and average FPGA power. CL designs can use power state pins to help developers throttle CL to avoid power violation.
• Improved IPI 3rd party simulator support
• Simulation model fixes
• SDAccel improvements - Removal of settings64 script from SDAccel setup and switching between DSAs

Release 1.3.4

• EDMA/XDMA Driver improvements
• Additional SDAccel Platforms
  • 1DDR for faster build times and smaller expanded shell
  • RTL Kernel Debug adds support for virtual jtag debug on RTL kernels
• IP Integrator GUI (HLx) improvements
• CL_DRAM_DMA fixes and improvements
  • Dual master support
• Simulation enviroment fixes and improvements
  • AXI/AXIL Protocol checkers
  • Shell model improvements
  • SW co-simulation support on cl_hello_world
  • DDR Model patch
• Updated SH_DDR module in preparation for upcoming feature release

Release 1.3.3

New FPGA Image APIs for deleting and reading/editing attributes

Release 1.3.2

SDAccel general availability

Release 1.3.1

Region expansion to DUB and PDX
AFI Copy API Preview
EDMA Driver release 1.0.29 - MSI-X fixes
Improved IPI documentation
Documentation updates
Build flow fixes
Public LTX files for use with hdk examples AFIs

Release 1.3.0

AWS EC2 FPGA HDK+SDK Release Notes

AWS EC2 F1 Platform Features:

• 1-8 Xilinx UltraScale+ VU9P based FPGA slots
• Per FPGA Slot, Interfaces available for Custom Logic(CL):
  • One x16 PCIe Gen 3 Interface
  • Four DDR4 RDIMM interfaces (with ECC)
  • AXI4 protocol support on all interfaces
• User-defined clock frequency driving all CL to Shell interfaces
• Multiple free running auxilary clocks
• PCIE endpoint presentation to Custom Logic(CL)
  • Management PF (physical function)
  • Application PF
• Virtual JTAG, Virtual LED, Virtual DIP Switches
• PCIE interface between Shell(SH) and Custom Logic(CL).
  • SH to CL inbound 512-bit AXI4 interface
  • CL to SH outbound 512-bit AXI4 interface
    * Multiple 32-bit AXI-Lite buses for register access, mapped to different PCIe BARs
  • Maximum payload size set by the Shell
  • Maximum read request size set by the Shell
  • AXI4 error handling
    * DDR interface between SH and CL
  • CL to SH 512-bit AXI4 interface
  • 1 DDR controller implemented in the SH (always available)
  • 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)

Release 1.3.0 (See ERRATA for unsupported features)

• FPGA initiated read/write over PCI (PCI-M)
• Redesigned Shell - improved the shell design to allow more complex place and route designs to meet timing
• Expanded DMA support
• Improved URAM utilization
• Improved AXI Interface checking
• New customer examples/workflows: IP Integrator, VHDL and GUI
• SDAccel support - More details will be communicated on AWS forum

During July, All AFIs created with previous HDK versions will no longer correctly load on an F1 instance, hence a fpga-load-local-image command executed with an AFI created prior to 1.3.0 will return an error and not load. Watch the forum for additional annnoucements.

Release 1.3.0 New Features Details

The following major features are included in this HDK release:

1. New Shell, with modified Shell/CL interface. Changes are covered in:

• The floorplan has been enhanced to enable more optimal CL designs through better timing closure and reduced congestion at the CL to Shell interface.
• New Shell Stable: v071417d3
• AWS_Shell_Interface_Specification.md has been updated. See cl_ports.vh for the updated port list
• DCP for the latest shell v071417d3. AWS Shell DCP is stored in S3 and fetched/verified when hdk_setup.sh script is sourced.

2. Integrated DMA

• DMA functionality has been enhanced to allow DMA transactions of up to 1MB.
• Multi-queue in each direction is now supported
• The DMA bus toward the CL is multiplexed over sh_cl_dma_pcis AXI4 interface so the same address space can be accessed via DMA or directly via PCIe AppPF BAR4
• DMA usage is covered in the new CL_DRAM_DMA example RTL verification/simulation and Software
• A corresponding AWS Elastic DMA (EDMA) driver is provided.
• EDMA Installation Readme provides installation and usage guidlines
• See Kernel_Drivers_README for more information on restrictions for this release

3. PCI-M

• The PCI-M interface is fully supported for CL generated transactions to the Shell.

4. URAM

• Restrictions on URAM have been updated to enable 100% of the URAM with a CL to be utilized. See documnetation on enabling URAM utilization: URAM_options

5. IPI

• IPI developer flow is supported

6. Build Flow improvments

• See Build_Scripts

7. VHDL

• CL designs in VHDL are fully supported.
  See example for more details CL_HELLO_WORLD_VHDL

8. AXI Interface Checking

• Protocol checks have been added to the CL-Shell interface to detect and report CL errors for enhanced CL debugging.
• Transaction timeout values on the CL-Shell interface have been increased to allow for longer CL response times.
• See Shell_Interface_Specification

9. Support for Vivado 2017.1 SDX Build

• The FPGA Development AMI includes Vivado 2017.1 SDX
  • Get the 1.3.0+ AMI by selecting the version from the marketplace.
• Older Vivado versions will not be supported

10. SDK changes

• Synchronous (default) mode for fpga-load-local-image and fpga-clear-local-image. For example, in synchronous mode (default) fpga-load-local-image will wait for the AFI to transition to the "loaded" state, perform a PCI device remove and recan in order to expose the unique AFI Vendor and Device Id, and display the final state for the given FPGA slot number. Asynchronous operation is preserved with the "-A" option to both fpga-load-local-image and fpga-clear-local-image.
• The corresponding fpga_mgmt_load_local_image_sync and fpga_mgmt_clear_local_image_sync are provided by the fpga_mgmt library for use in C/C++ programs.

Supported Tools and Environment

• The HDK and SDK are designed for Linux environment and has not been tested on other platforms
• First installation of AWS FPGA SDK requires having gcc installed in the instance server. If that's not available, try sudo yum update && sudo yum group install "Development Tools"
• The HDK build step requires having Xilinx's Vivado tool and Vivado License Management running. Tools and licenses are provided with AWS FPGA Developer AMI at no additional cost
• This release is tested and validated with Xilinx 2017.1 SDX (Vivado)
• Developers that choose to not use the developer AMI in AWS EC2, need to have Xilinx license 'EF-VIVADO-SDX-VU9P-OP' installed on premise. For more help, please refer to On-premise licensing help
• Vivado XSIM RTL simulator supported by the HDK
• MentorGraphic's Questa RTL simulator supported by the HDK (but requires a purchase of separate license from MentorGraphics)
• Synopsys' VCS RTL simulator supported by the HDK (but requires a purchase of separate license from Synopsys)

License Requirements

The HDK and SDK in the development kit have different licenses. SDK is licensed under open source Apache license and HDK is licensed under Amazon Software License. Please refer to HDK License and SDK License.

Release Notes FAQ

**Q: How do I know which HDK version I have on my instance/machine? **

Look for hdk_version

**Q: How do I know what my Shell Version is? **

The Shell Version of an instance is available through the FPGA Image Management tools. See the description of fpga-describe-local-image for details on retrieving the shell version from an instance.

**Q: How do I know what version of FPGA Image management tools are running on my instance? **

The FPGA Image management tools version is reported with any command executed to those tools. See the description of fpga-describe-local-image for details on the tools version identification.

Q: How do I update my design with this release?

1. Start by either cloning the entire GitHub structure for the HDK release or downloading new directories that have changed. AWS recommends an entire GitHub clone to ensure no files are missed
2. Update the CL design to conform to the new AWS_Shell_Interface_Specification
3. Follow the process for AFI generation outlined in aws-fpga/hdk/cl/examples/readme.md
4. Update FPGA Image Management Tools to the version included in aws-fpga/sdk/management

Q: How do I get support for this release?

The AWS Forum FPGA Development provides an easy access to Developer support. The FPGA development user forum is the first place to go to post questions, suggestions and receive important announcements. To gain access to the user forum, please go to https://forums.aws.amazon.com/index.jspa and login. To be notified on important messages, posts you will need to click the “Watch Forum” button on the right side of the screen.

**Q: How do I know which HDK release I am working with? **

See the release notes at the top of the GitHub directory to identify the version of your GitHub clone.

Previous release notes

Release 1.2.4

• AWS SDK API aws ec2 describe-fpga-images released. See describe-fpga-images document for details on how to use this API. Requires Developer AMI 1.2.4 or awscli upgrade: pip install --upgrade --user awscli
• Fix cl_dram_dam debug probes (.ltx) generation in build scripts
• Fixed bugs with DMA in the simulation model and testbench

Release 1.2.3

• New Errata
• Added debug probes (.ltx) generation to build scripts
• Fixed a bug with the simulation model that fixed the AXI behavior of wlast on unaligned address
• Added timeout debug documentation

Release 1.2.2

• Expanded clock recipes
• Virtual JTAG documentation updates
• Reduced DCP build times by 13% (34 mins) for cl_dram_dma example by adding an option to disable virtual jtag
• Included encryption of .sv files for CL examples

Release 1.2.1

• Updated CL example build scripts with Prohibit URAM sites
• EDMA Performance improvments
• Expanded EC2 Instance type support
  ...

Release 1.2.5

• Improved tool checks in hdk_setup
• Fixed simulation model and test bench bugs