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Feature: Initial RISC-V debug support (v0.13 spec) #1380

Merged
merged 62 commits into from
Oct 31, 2023
Merged

Feature: Initial RISC-V debug support (v0.13 spec) #1380

merged 62 commits into from
Oct 31, 2023

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dragonmux
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@dragonmux dragonmux commented Feb 11, 2023

Detailed description

In this PR we implement support for debugging RISC-V targets complying with v0.13.2 of the RISC-V debug specification. This includes support for both rv32 and rv64 targets and intentionally fails to work with rv128 targets (though we still must detect those).

This PR also introduces support for the GD32VF1 series through minimal changes to stm32f1.c, providing a test target to play with.

Known limitations include:

  • The target must support both abstract register and abstract memory access commands. Reasonable hook points have been left in riscv32.c and riscv64.c to implement system bus access for memory commands in the future. This will probably be addressed in a follow-up PR as using the system bus is not that difficult and determining if it can be used is a trivial DM register write/read.
  • RISC-V debug spec v1.0 targets are likely only partially functional (the DMI is the same, but the DM contains differences not addressed here)
  • RISC-V debug spec v0.11 devices will not work with this. The correct specification SiFive used in early devices is referenced but support is not addressed at this time.

This PR replaces #924.

Your checklist for this pull request

  • I've read the Code of Conduct
  • I've read the guidelines for contributing to this repository
  • It builds for hardware native (make PROBE_HOST=native)
  • It builds as BMDA (make PROBE_HOST=hosted)
  • I've tested it to the best of my ability
  • My commit messages provide a useful short description of what the commits do

Closing issues

Fixes #794

@dragonmux dragonmux added Enhancement General project improvement New Target New debug target labels Feb 11, 2023
@dragonmux dragonmux added this to the v2.0 release milestone Feb 11, 2023
@dragonmux dragonmux requested a review from esden February 11, 2023 07:23
@dragonmux dragonmux force-pushed the feature/risc-v branch 4 times, most recently from 2f979c6 to a7f8493 Compare February 12, 2023 08:30
@dragonmux dragonmux mentioned this pull request Feb 12, 2023
6 tasks
@dragonmux dragonmux force-pushed the feature/risc-v branch 3 times, most recently from e83a3c4 to 6d26f71 Compare March 28, 2023 02:25
@dragonmux dragonmux force-pushed the feature/risc-v branch 4 times, most recently from 70bfb82 to f37451f Compare April 4, 2023 08:04
@dragonmux dragonmux force-pushed the feature/risc-v branch 2 times, most recently from 6c4e7da to b13aafb Compare April 17, 2023 03:13
@dragonmux dragonmux force-pushed the feature/risc-v branch 2 times, most recently from 2da4783 to 26d0935 Compare June 6, 2023 05:25
@dragonmux dragonmux force-pushed the feature/risc-v branch 2 times, most recently from a3817aa to 69874a2 Compare June 22, 2023 05:13
@dragonmux dragonmux force-pushed the feature/risc-v branch 3 times, most recently from de4fc3d to 488cdea Compare July 7, 2023 00:17
@dragonmux dragonmux force-pushed the feature/risc-v branch 2 times, most recently from 51957f7 to fbec35e Compare July 20, 2023 07:07
dragonmux and others added 25 commits October 31, 2023 05:31
…djust for BMD's representation of JEP-106 codes
…ose some CSRs register in the xml description
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Fantastic! Finally! Thank you!

@esden esden merged commit 1566256 into main Oct 31, 2023
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@dragonmux dragonmux deleted the feature/risc-v branch October 31, 2023 05:44
@dragonmux dragonmux mentioned this pull request Nov 30, 2023
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Is it possible to support riscv arch?
3 participants