Fix GCC warnings

src/Makefile

@@ -21,8 +21,14 @@ ifeq (filter, macosx darwin, $(SYS))
 CFLAGS += -Wmaybe-uninitialized -Wstringop-overflow -Wunsafe-loop-optimizations
 endif
 
+ifeq ($(PROBE_HOST),hosted)
+ENABLE_DEBUG := 1
+endif
+
 ifeq ($(ENABLE_DEBUG), 1)
-CFLAGS += -DENABLE_DEBUG
+CFLAGS += -DENABLE_DEBUG=1
+else
+CFLAGS += -DENABLE_DEBUG=0
 endif
 
 SRC =              \
@@ -144,6 +150,8 @@ endif
 
 ifeq ($(ADVERTISE_NOACKMODE), 1)
 CFLAGS += -DADVERTISE_NOACKMODE=1
+else
+CFLAGS += -DADVERTISE_NOACKMODE=0
 endif
 
 OBJ = $(patsubst %.S,%.o,$(patsubst %.c,%.o,$(SRC)))

src/crc32.c

@@ -113,7 +113,7 @@ bool generic_crc32(target_s *const target, uint32_t *const result, const uint32_
 	uint8_t bytes[128U];
 #endif
 
-#if defined(ENABLE_DEBUG)
+#if ENABLE_DEBUG == 1
 	const uint32_t start_time = platform_time_ms();
 #endif
 	uint32_t last_time = platform_time_ms();

src/include/gdb_if.h

@@ -21,7 +21,7 @@
 #ifndef INCLUDE_GDB_IF_H
 #define INCLUDE_GDB_IF_H
 
-#if PC_HOSTED == 0
+#if PC_HOSTED == 0 && !defined(NO_LIBOPENCM3)
 #include <libopencm3/usb/usbd.h>
 void gdb_usb_out_cb(usbd_device *dev, uint8_t ep);
 #endif

src/include/gdb_main.h

@@ -31,6 +31,6 @@ extern target_s *cur_target;
 void gdb_poll_target(void);
 void gdb_main(char *pbuf, size_t pbuf_size, size_t size);
 int gdb_main_loop(target_controller_s *tc, char *pbuf, size_t pbuf_size, size_t size, bool in_syscall);
-char *gdb_packet_buffer();
+char *gdb_packet_buffer(void);
 
 #endif /* INCLUDE_GDB_MAIN_H */

src/include/general.h

@@ -81,7 +81,12 @@
 #define PRINT_NOOP(...) \
 	do {                \
 	} while (false)
-#if defined(ENABLE_DEBUG)
+
+#ifndef ENABLE_DEBUG
+#define ENABLE_DEBUG 0
+#endif
+
+#if ENABLE_DEBUG == 1
 #define DEBUG_ERROR(...) PLATFORM_PRINTF(__VA_ARGS__)
 #define DEBUG_WARN(...)  PLATFORM_PRINTF(__VA_ARGS__)
 #define DEBUG_INFO(...)  PLATFORM_PRINTF(__VA_ARGS__)

src/include/rtt_if.h

@@ -68,8 +68,8 @@ int rtt_if_exit(void);
 /* target to host: write len bytes from the buffer starting at buf. return number bytes written */
 uint32_t rtt_write(const char *buf, uint32_t len);
 /* host to target: read one character, non-blocking. return character, -1 if no character */
-int32_t rtt_getchar();
+int32_t rtt_getchar(void);
 /* host to target: true if no characters available for reading */
-bool rtt_nodata();
+bool rtt_nodata(void);
 
 #endif /* INCLUDE_RTT_IF_H */

src/platforms/common/aux_serial.h

@@ -69,7 +69,7 @@ void aux_serial_send(size_t len);
 void aux_serial_update_receive_buffer_fullness(void);
 bool aux_serial_receive_buffer_empty(void);
 void aux_serial_drain_receive_buffer(void);
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 void aux_serial_stage_debug_buffer(void);
 #endif
 void aux_serial_stage_receive_buffer(void);

src/platforms/common/usb_serial.c

@@ -40,7 +40,7 @@
  *
  */
 
-#ifndef ENABLE_DEBUG
+#if ENABLE_DEBUG != 1
 #include <sys/stat.h>
 #include <string.h>
 
@@ -77,7 +77,7 @@ static void debug_serial_receive_callback(usbd_device *dev, uint8_t ep);
 static bool debug_serial_send_complete = true;
 #endif
 
-#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
+#if ENABLE_DEBUG == 1 && defined(PLATFORM_HAS_DEBUG)
 /*
  * This call initialises "SemiHosting", only we then do our own SVC interrupt things to
  * route all output through to the debug USB serial interface if debug_bmp is true.
@@ -214,7 +214,7 @@ void usb_serial_set_config(usbd_device *dev, uint16_t value)
 	usb_serial_set_state(dev, GDB_IF_NO, CDCACM_GDB_ENDPOINT + 1U);
 	usb_serial_set_state(dev, UART_IF_NO, CDCACM_UART_ENDPOINT + 1U);
 
-#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
+#if ENABLE_DEBUG == 1 && defined(PLATFORM_HAS_DEBUG)
 	initialise_monitor_handles();
 #endif
 }
@@ -249,7 +249,7 @@ uint32_t debug_serial_fifo_send(const char *const fifo, const uint32_t fifo_begi
 	return fifo_begin;
 }
 
-#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
+#if ENABLE_DEBUG == 1 && defined(PLATFORM_HAS_DEBUG)
 static bool debug_serial_fifo_buffer_empty(void)
 {
 	return debug_serial_debug_write_index == debug_serial_debug_read_index;
@@ -270,17 +270,17 @@ static void debug_serial_send_data(void)
 	 * If fifo empty, nothing further to do. */
 	if (usb_get_config() != 1 ||
 		(aux_serial_receive_buffer_empty()
-#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
+#if ENABLE_DEBUG == 1 && defined(PLATFORM_HAS_DEBUG)
 			&& debug_serial_fifo_buffer_empty()
 #endif
 				)) {
-#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
+#if ENABLE_DEBUG == 1 && defined(PLATFORM_HAS_DEBUG)
 		debug_serial_debug_read_index = debug_serial_debug_write_index;
 #endif
 		aux_serial_drain_receive_buffer();
 		debug_serial_send_complete = true;
 	} else {
-#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
+#if ENABLE_DEBUG == 1 && defined(PLATFORM_HAS_DEBUG)
 		debug_serial_debug_read_index = debug_serial_fifo_send(
 			debug_serial_debug_buffer, debug_serial_debug_read_index, debug_serial_debug_write_index);
 #endif
@@ -339,7 +339,7 @@ static void debug_serial_receive_callback(usbd_device *dev, uint8_t ep)
 #endif
 }
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 #ifdef PLATFORM_HAS_DEBUG
 static void debug_serial_append_char(const char c)
 {

src/platforms/f072/platform.h

@@ -133,7 +133,7 @@
 #define TRACE_IRQ          NVIC_TIM3_IRQ
 #define TRACE_ISR          tim3_isr
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 extern bool debug_bmp;
 #define DEBUG printf
 #else

src/platforms/f3/platform.h

@@ -126,7 +126,7 @@
 #define TRACE_IRQ          NVIC_TIM3_IRQ
 #define TRACE_ISR          tim3_isr
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 extern bool debug_bmp;
 #define DEBUG printf
 #else

src/platforms/hosted/Makefile.inc

@@ -2,7 +2,7 @@ ifeq ($(origin CC),default)
     CC := gcc
 endif
 SYS := $(shell $(CC) -dumpmachine)
-CFLAGS += -DENABLE_DEBUG -DPLATFORM_HAS_DEBUG
+CFLAGS += -DPLATFORM_HAS_DEBUG
 CFLAGS +=-I ./target
 
 ENABLE_CORTEXAR := 1

src/platforms/hosted/dap_jtag.c

@@ -108,7 +108,7 @@ static void dap_jtag_tdi_seq(const bool final_tms, const uint8_t *const data_in,
 
 static bool dap_jtag_next(const bool tms, const bool tdi)
 {
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 	const uint8_t tms_byte = tms ? 1 : 0;
 #endif
 	const uint8_t tdi_byte = tdi ? 1 : 0;

src/platforms/native/platform.h

@@ -30,7 +30,7 @@
 #define PLATFORM_HAS_TRACESWO
 #define PLATFORM_HAS_POWER_SWITCH
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 #define PLATFORM_HAS_DEBUG
 extern bool debug_bmp;
 #endif

src/platforms/stlink/platform.h

@@ -31,7 +31,7 @@
 #include <libopencm3/stm32/memorymap.h>
 #include <libopencm3/usb/usbd.h>
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 #define PLATFORM_HAS_DEBUG
 extern bool debug_bmp;
 #endif

src/platforms/stlinkv3/platform.h

@@ -32,7 +32,7 @@
 #include <libopencm3/stm32/f1/memorymap.h>
 #include <libopencm3/usb/usbd.h>
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 #define PLATFORM_HAS_DEBUG
 extern bool debug_bmp;
 #endif

src/platforms/swlink/platform.h

@@ -28,7 +28,7 @@
 #include "timing.h"
 #include "timing_stm32.h"
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 #define PLATFORM_HAS_DEBUG
 extern bool debug_bmp;
 #endif

src/remote.c

@@ -317,7 +317,7 @@ static void remote_packet_process_general(char *packet, const size_t packet_len)
 #endif
 		break;
 	case REMOTE_START:
-#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
+#if ENABLE_DEBUG == 1 && defined(PLATFORM_HAS_DEBUG)
 		debug_bmp = true;
 #endif
 		remote_respond_string(REMOTE_RESP_OK, PLATFORM_IDENT "" FIRMWARE_VERSION);

src/target/adiv5.c

@@ -126,7 +126,7 @@ typedef enum arm_arch {
 	aa_end
 } arm_arch_e;
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 #define ARM_COMPONENT_STR(...) __VA_ARGS__
 #else
 #define ARM_COMPONENT_STR(...)
@@ -177,7 +177,7 @@ static const struct {
 	uint16_t arch_id;
 	arm_arch_e arch;
 	cid_class_e cidc;
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 	const char *type;
 	const char *full;
 #endif
@@ -272,7 +272,7 @@ static const struct {
 	{0xfff, 0x00, 0, aa_end, cidc_unknown, ARM_COMPONENT_STR("end", "end")},
 };
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 static const char *adiv5_arm_ap_type_string(const uint8_t ap_type, const uint8_t ap_class)
 {
 	/*
@@ -543,7 +543,7 @@ static void adiv5_component_probe(
 		return;
 	}
 
-#if defined(ENABLE_DEBUG)
+#if ENABLE_DEBUG == 1
 	char *indent = alloca(recursion + 1U);
 
 	for (size_t i = 0; i < recursion; i++)
@@ -608,7 +608,7 @@ static void adiv5_component_probe(
 			}
 		}
 
-#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
+#if ENABLE_DEBUG == 1 && defined(PLATFORM_HAS_DEBUG)
 		/* Check SYSMEM bit */
 		const uint32_t memtype = adiv5_mem_read32(ap, addr | ADIV5_ROM_MEMTYPE) & ADIV5_ROM_MEMTYPE_SYSMEM;
 
@@ -747,7 +747,7 @@ adiv5_access_port_s *adiv5_new_ap(adiv5_debug_port_s *dp, uint8_t apsel)
 
 	memcpy(ap, &tmpap, sizeof(*ap));
 
-#if defined(ENABLE_DEBUG)
+#if ENABLE_DEBUG == 1
 	/* Grab the config register to get a complete set */
 	uint32_t cfg = adiv5_ap_read(ap, ADIV5_AP_CFG);
 	DEBUG_INFO("AP %3u: IDR=%08" PRIx32 " CFG=%08" PRIx32 " BASE=%08" PRIx32 " CSW=%08" PRIx32, apsel, ap->idr, cfg,

src/target/adiv5_swd.c

@@ -19,7 +19,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/* 
+/*
  * This file implements the SWD specific functions of the
  * ARM Debug Interface v5 Architecture Specification, ARM doc IHI0031A.
  */
@@ -67,7 +67,7 @@ static void swd_line_reset_sequence(const bool idle_cycles)
 }
 
 /* Switch out of dormant state into SWD */
-static void dormant_to_swd_sequence()
+static void dormant_to_swd_sequence(void)
 {
 	/*
 	 * ARM Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2. ARM IHI 0031C
@@ -102,7 +102,7 @@ static void dormant_to_swd_sequence()
 }
 
 /* Deprecated JTAG-to-SWD select sequence */
-static void jtag_to_swd_sequence()
+static void jtag_to_swd_sequence(void)
 {
 	/*
 	 * ARM Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2. ARM IHI 0031C

src/target/cortexar.c

@@ -964,7 +964,7 @@ static void cortexr_mem_handle_fault(
 	const cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
 	/* If we suffered a fault of some kind, grab the reason and restore DFSR/DFAR */
 	if (priv->core_status & CORTEXAR_STATUS_DATA_FAULT) {
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 		const uint32_t fault_status = cortexar_coproc_read(target, CORTEXAR_DFSR);
 		const uint32_t fault_addr = cortexar_coproc_read(target, CORTEXAR_DFAR);
 #else

src/target/cortexm.c

@@ -117,7 +117,7 @@ typedef struct cortexm_priv {
 	uint32_t demcr;
 } cortexm_priv_s;
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 const char *const semihosting_names[] = {
 	"",
 	"SYS_OPEN",
@@ -1470,7 +1470,7 @@ static int cortexm_hostio_request(target_s *target)
 		target_mem_read(target, params, arm_regs[1], sizeof(params));
 	int32_t ret = 0;
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 	const char *syscall_descr = NULL;
 	if (syscall < ARRAY_LENGTH(semihosting_names))
 		syscall_descr = semihosting_names[syscall];

src/target/efm32.c

@@ -656,7 +656,7 @@ static bool efm32_flash_write(target_flash_s *f, target_addr_t dest, const void
 	/* Run flashloader */
 	const bool ret = cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, priv_storage->device->msc_addr) == 0;
 
-#ifdef ENABLE_DEBUG
+#if ENABLE_DEBUG == 1
 	/* Check the MSC_IF */
 	uint32_t msc = priv_storage->device->msc_addr;
 	uint32_t msc_if = target_mem_read32(t, EFM32_MSC_IF(msc));

src/target/imxrt.c

@@ -218,7 +218,7 @@ bool imxrt_probe(target_s *const target)
 	snprintf(priv->name, IMXRT_NAME_MAX_LENGTH, "i.MXRT%u", priv->chip_id);
 	target->driver = priv->name;
 
-#if defined(ENABLE_DEBUG) && (PC_HOSTED == 1 || defined(ESP_LOGD))
+#if ENABLE_DEBUG == 1 && (PC_HOSTED == 1 || defined(ESP_LOGD))
 	const uint8_t boot_mode = (target_mem_read32(target, IMXRT_SRC_BOOT_MODE2) >> 24U) & 3U;
 #endif
 	DEBUG_TARGET("i.MXRT boot mode is %x\n", boot_mode);
@@ -521,7 +521,7 @@ static void imxrt_spi_wait_complete(target_s *const target)
 	target_mem_write32(target, IMXRT_FLEXSPI1_INT(priv), IMXRT_FLEXSPI1_INT_PRG_CMD_DONE);
 	/* Check if any errors occured */
 	if (target_mem_read32(target, IMXRT_FLEXSPI1_INT(priv)) & IMXRT_FLEXSPI1_INT_CMD_ERR) {
-#if defined(ENABLE_DEBUG) && PC_HOSTED == 1
+#if ENABLE_DEBUG == 1 && PC_HOSTED == 1
 		/* Read out the status code and display it */
 		const uint32_t status = target_mem_read32(target, IMXRT_FLEXSPI1_STAT1(priv));
 		DEBUG_TARGET("Error executing sequence, offset %u, error code %u\n", (uint8_t)(status >> 16U) & 0xfU,