Feature: Zynq-7000 support

src/Makefile

@@ -84,7 +84,8 @@ SRC =              \
 	renesas.c      \
 	target.c       \
 	target_flash.c \
-	target_probe.c
+	target_probe.c \
+	zynq7000.c
 
 ifeq (,$(filter all_platforms,$(MAKECMDGOALS)))
 include $(PLATFORM_DIR)/Makefile.inc

src/target/adiv5.c

@@ -206,7 +206,7 @@ static const struct {
 	{0x908, 0x12, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight CSTF", "(Trace Funnel)")},
 	{0x910, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight ETM9", "(Embedded Trace)")},
 	{0x912, 0x11, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight TPIU", "(Trace Port Interface Unit)")},
-	{0x913, 0x00, 0, aa_nosupport, cidc_unknown,
+	{0x913, 0x43, 0, aa_nosupport, cidc_unknown,
 		ARM_COMPONENT_STR("CoreSight ITM", "(Instrumentation Trace Macrocell)")},
 	{0x914, 0x11, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight SWO", "(Single Wire Output)")},
 	{0x917, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight HTM", "(AHB Trace Macrocell)")},
@@ -221,8 +221,7 @@ static const struct {
 		ARM_COMPONENT_STR("CoreSight MTB-M0+", "(Simple Execution Trace)")},
 	{0x941, 0x00, 0, aa_nosupport, cidc_unknown,
 		ARM_COMPONENT_STR("CoreSight TPIU-Lite", "(Trace Port Interface Unit)")},
-	{0x950, 0x00, 0, aa_nosupport, cidc_unknown,
-		ARM_COMPONENT_STR("CoreSight Component", "(unidentified Cortex-A9 component)")},
+	{0x950, 0x13, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A9 PTM", "(Program Trace Macrocell)")},
 	{0x955, 0x00, 0, aa_nosupport, cidc_unknown,
 		ARM_COMPONENT_STR("CoreSight Component", "(unidentified Cortex-A5 component)")},
 	{0x956, 0x13, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A7 ETM", "(Embedded Trace)")},
@@ -232,7 +231,7 @@ static const struct {
 	{0x962, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight STM", "(System Trace Macrocell)")},
 	{0x963, 0x63, 0x0a63, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight STM", "(System Trace Macrocell)")},
 	{0x975, 0x13, 0x4a13, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M7 ETM", "(Embedded Trace)")},
-	{0x9a0, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight PMU", "(Performance Monitoring Unit)")},
+	{0x9a0, 0x16, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("CoreSight PMU", "(Performance Monitoring Unit)")},
 	{0x9a1, 0x11, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M4 TPIU", "(Trace Port Interface Unit)")},
 	{0x9a6, 0x14, 0x1a14, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M0+ CTI", "(Cross Trigger Interface)")},
 	{0x9a9, 0x11, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-M7 TPIU", "(Trace Port Interface Unit)")},
@@ -242,7 +241,7 @@ static const struct {
 	{0xc05, 0x00, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A5 Debug", "(Debug Unit)")},
 	{0xc07, 0x15, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A7 Debug", "(Debug Unit)")},
 	{0xc08, 0x00, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A8 Debug", "(Debug Unit)")},
-	{0xc09, 0x00, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A9 Debug", "(Debug Unit)")},
+	{0xc09, 0x15, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A9 Debug", "(Debug Unit)")},
 	{0xc0f, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A15 Debug", "(Debug Unit)")}, /* support? */
 	{0xc14, 0x15, 0, aa_cortexr, cidc_unknown, ARM_COMPONENT_STR("Cortex-R4", "(Debug Unit)")},
 	{0xcd0, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Atmel DSU", "(Device Service Unit)")},

src/target/cortexar.c

@@ -812,6 +812,9 @@ bool cortexa_probe(adiv5_access_port_s *const ap, const target_addr_t base_addre
 	case JEP106_MANUFACTURER_STM:
 		PROBE(stm32mp15_ca7_probe);
 		break;
+	case JEP106_MANUFACTURER_XILINX:
+		PROBE(zynq7_probe);
+		break;
 	}
 
 #if PC_HOSTED == 0

src/target/jep106.h

@@ -67,7 +67,7 @@
 #define JEP106_MANUFACTURER_GIGADEVICE   0x751U /* GigaDevice */
 #define JEP106_MANUFACTURER_RASPBERRY    0x913U /* Raspberry Pi */
 #define JEP106_MANUFACTURER_RENESAS      0x423U /* Renesas */
-#define JEP106_MANUFACTURER_XILINX       0x309U /* Xilinx */
+#define JEP106_MANUFACTURER_XILINX       0x309U /* Xilinx - Technically 0x049, but they use Ikanos Communications' code */
 /*
  * This JEP code should belong to "Andes Technology Corporation", but is used on RISC-V by GigaDevice,
  * so in the unlikely event we need to support chips by them, here be dragons.

src/target/target_probe.c

@@ -125,5 +125,6 @@ TARGET_PROBE_WEAK_NOP(renesas_probe)
 TARGET_PROBE_WEAK_NOP(mm32l0xx_probe)
 TARGET_PROBE_WEAK_NOP(mm32f3xx_probe)
 TARGET_PROBE_WEAK_NOP(imxrt_probe)
+TARGET_PROBE_WEAK_NOP(zynq7_probe)
 
 LPC55_DP_PREPARE_WEAK_NOP(lpc55_dp_prepare)

src/target/target_probe.h

@@ -93,6 +93,7 @@ bool ke04_probe(target_s *target);
 bool rp_probe(target_s *target);
 bool renesas_probe(target_s *target);
 bool imxrt_probe(target_s *target);
+bool zynq7_probe(target_s *target);
 
 void lpc55_dp_prepare(adiv5_debug_port_s *dp);
 

src/target/zynq7000.c

@@ -0,0 +1,118 @@
+/*
+ * This file is part of the Black Magic Debug project.
+ *
+ * Copyright (C) 2023 1BitSquared <[email protected]>
+ * Written by Rachel Mant <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file implement support for the Zynq-7000 series devices, providing
+ * memory maps, and other utility routines.
+ *
+ * NB: This handles the ARM cores only, not the PL.
+ *
+ * References:
+ * UG585 - Zynq 7000 SoC Technical Reference Manual
+ *   https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM
+ *   https://docs.xilinx.com/api/khub/maps/mxcNFn1EFZjLI1eShoEn5w/attachments/pnoMLQXFIWQ6Jhoj0BUsTQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=4.2.13&download=true
+ */
+
+#include "general.h"
+#include "target.h"
+#include "target_internal.h"
+#include "cortex_internal.h"
+#include "exception.h"
+
+#define CORTEXA_DBG_IDR 0x000U
+
+/* On-Chip Memory (OCM) region definitions */
+#define ZYNQ7_OCM_LOW_BASE   0x00000000U
+#define ZYNQ7_OCM_HIGH_BASE  0xfffc0000U
+#define ZYNQ7_OCM_CHUNK_SIZE 0x00010000U
+
+/* System Level Control Registers */
+#define ZYNQ7_SLCR_BASE         0xf8000000U
+#define ZYNQ7_SLCR_UNLOCK       (ZYNQ7_SLCR_BASE + 0x008U)
+#define ZYNQ7_SLCR_PSS_RST_CTRL (ZYNQ7_SLCR_BASE + 0x200U)
+#define ZYNQ7_SLCR_OCM_CFG      (ZYNQ7_SLCR_BASE + 0x910U)
+
+/* UG585 Appendix A: Register Details, pg1639 */
+#define ZYNQ7_SLCR_UNLOCK_KEY 0x0000df0dU
+/* UG585 Appendix A: Register Details, pg1672 */
+#define ZYNQ7_SLCR_PSS_RST_CTRL_SOFT_RESET (1U << 0U)
+
+static void zynq7_reset(target_s *target);
+
+#define ID_ZYNQ7020 0x3b2U
+
+bool zynq7_probe(target_s *const target)
+{
+	if (target->part_id != ID_ZYNQ7020)
+		return false;
+
+	target->driver = "Zynq-7000";
+	target->reset = zynq7_reset;
+
+	/* Read back the OCM mapping status */
+	const uint8_t ocm_mapping = target_mem_read32(target, ZYNQ7_SLCR_OCM_CFG) & 0x0fU;
+	/* For each of the 4 chunks, pull out if it's mapped low or high and define a mapping accordingly */
+	for (uint8_t chunk = 0U; chunk < 4U; ++chunk) {
+		const bool chunk_high = (ocm_mapping >> chunk) & 1U;
+		const uint32_t chunk_offset = chunk * ZYNQ7_OCM_CHUNK_SIZE;
+		target_add_ram(
+			target, (chunk_high ? ZYNQ7_OCM_HIGH_BASE : ZYNQ7_OCM_LOW_BASE) + chunk_offset, ZYNQ7_OCM_CHUNK_SIZE);
+	}
+
+	return true;
+}
+
+static void zynq7_reset(target_s *const target)
+{
+	/* Try to unlock the SLCR registers and issue the reset */
+	target_mem_write32(target, ZYNQ7_SLCR_UNLOCK, ZYNQ7_SLCR_UNLOCK_KEY);
+	target_mem_write32(target, ZYNQ7_SLCR_PSS_RST_CTRL, ZYNQ7_SLCR_PSS_RST_CTRL_SOFT_RESET);
+
+	/* For good measure, also try pulsing the physical reset pin */
+	platform_nrst_set_val(true);
+	platform_nrst_set_val(false);
+
+	/* Spin until the Zynq comes back up */
+	platform_timeout_s reset_timeout;
+	platform_timeout_set(&reset_timeout, 1000U);
+	volatile exception_s error = {.type = EXCEPTION_ERROR};
+	while (error.type == EXCEPTION_ERROR && !platform_timeout_is_expired(&reset_timeout)) {
+		/* Try doing a new read of the core's ID register */
+		TRY_CATCH (error, EXCEPTION_ALL) {
+			cortex_dbg_read32(target, CORTEXA_DBG_IDR);
+		}
+	}
+	/* If that failed, propagate the error */
+	if (error.type == EXCEPTION_ERROR)
+		raise_exception(error.type, error.msg);
+}