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Fix MCL binary signal handling (call reset() in mcl_step()).
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Signed-off-by: Timothy Rule (VM/EMT3) <[email protected]>
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timrulebosch committed Nov 6, 2024
1 parent 3dde623 commit fcbb17f
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Showing 2 changed files with 15 additions and 3 deletions.
2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ TOOL_DIRS = simer
################
## DSE Projects.
DSE_CLIB_REPO ?= https://github.com/boschglobal/dse.clib
DSE_CLIB_VERSION ?= 1.0.21
DSE_CLIB_VERSION ?= 1.0.22
export DSE_CLIB_URL ?= $(DSE_CLIB_REPO)/archive/refs/tags/v$(DSE_CLIB_VERSION).zip

DSE_SCHEMA_REPO ?= https://github.com/boschglobal/dse.schemas
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16 changes: 14 additions & 2 deletions dse/modelc/model/mcl.c
Original file line number Diff line number Diff line change
Expand Up @@ -120,9 +120,9 @@ static void _match_block(MclDesc* model, HashList* msm_list, size_t offset,
hashlist_append(msm_list, msm);

/* Logging. */
log_notice("FMU <-> SignalVector mapping for: %s", msm->name);
log_notice("SignalVector <-> MCL mapping for: %s", msm->name);
for (uint32_t i = 0; i < msm->count; i++) {
log_notice(" Variable: %s (%d) <-> %s (%d)",
log_notice(" Signal: %s (%d) <-> %s (%d)",
sv->signal[msm->signal.index[i]], msm->signal.index[i],
model->source.signal[msm->source.index[i]],
msm->source.index[i]);
Expand Down Expand Up @@ -250,6 +250,15 @@ int32_t mcl_step(MclDesc* model, double end_time)
int rc;

if (model && model->vtable.step) {
/* Reset binary signals. */
for (SignalVector* sv = model->model.sv; sv && sv->name; sv++) {
if (sv->is_binary) {
for (uint32_t i = 0; i < sv->count; i++) {
signal_reset(sv, i);
}
}
}

/* Calculate epsilon value (if necessary). */
if (model->step_size) mcl_epsilon = model->step_size * 0.01;

Expand Down Expand Up @@ -282,6 +291,9 @@ int32_t mcl_step(MclDesc* model, double end_time)
rc =
model->vtable.step(model, &model_current_time, model_stop_time);
model->model_time = model_current_time;

// FIXME: when MCL Target is stepped multiple times, it will be
// necessary to marshal in binary signals after each step.
} while (model_stop_time + mcl_epsilon < end_time);

return rc;
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