Literature is a luxury; fiction is a necessity

.gitattributes

@@ -0,0 +1,6 @@
+benchmarks/* linguist-vendored
+benchmarks/TOY/* linguist-vendored
+benchmarks/ISCAS89/* linguist-vendored
+benchmarks/EPFL/* linguist-vendored
+benchmarks/ITC99/* linguist-vendored
+*.v linguist-detectable=false

CHANGELOG.md

@@ -0,0 +1,32 @@
+# Changelog
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/).
+
+## v0.1.1 - 2018-12-29
+*Literature is a luxury; fiction is a necessity.* — G. K. Chesterton
+### Added
+- Technology-specific energy model for fcn_gate_layout; supports QCA thus far
+- Support for `print -c` to write a textual representation of fcn_cell_layout objects
+- Information on nested fiction scripts and documentation generation in README
+- *linguist* flags in .gitattributes to prevent benchmark files from being viewed as source code
+
+### Changed
+- Moved to version 0.4 of [Alice](https://github.com/msoeken/alice)
+- Moved to version 4.8.4 of [Z3](https://github.com/Z3Prover/z3)
+- `fcn_gate_library` objects now have name strings
+- `print -g` now displays incorrectly assigned directions by bidirectional arrows
+- "Release" is the standard build mode now
+
+### Fixed
+- Copy and move constructors of logic_network work properly now
+- Calculation of bounding_box size on fcn_gate_layout now handles empty layouts correctly
+- Several minor and rare bugs, code inconsistencies, and performance issues
+
+### Removed
+- Nothing
+
+## v0.1.0 - 2018-10-29
+*Let there be a fiction*
+
+This is the initial release. Please find a feature overview in the README.

CMakeLists.txt

@@ -1,15 +1,21 @@
 cmake_minimum_required(VERSION 3.2)
 project(fiction
         LANGUAGES CXX
-        VERSION 0.1)
+        VERSION 0.1.1)
 
 # C++14
 set(CMAKE_CXX_STANDARD 14)
 
 # Set debug build options
 set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -Wall -Wextra -Wpedantic")
 # Set release build options
-set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -Wall -O3")
+set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -w -O3")
+# Set release mode to default
+if (NOT CMAKE_BUILD_TYPE OR CMAKE_BUILD_TYPE STREQUAL "")
+    set(CMAKE_BUILD_TYPE "Release" CACHE STRING "" FORCE)
+endif()
+# Set the possible values of build type for cmake-gui
+set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS "Debug" "Release")
 
 # Include header files
 include_directories(include/)
@@ -59,6 +65,7 @@ add_subdirectory(${LIB_PREFIX}/lorina/)
 
 # build executable
 add_executable(fiction ${SOURCES} ${HEADERS})
+add_dependencies(fiction z3)
 
 # link against Boost, Z3, alice, and lorina
 target_link_libraries(fiction ${Boost_LIBRARIES} ${Z3_DIR}/lib/libz3.so alice lorina)

README.md

@@ -42,8 +42,8 @@ If you are on *Ubuntu*, you should be fine installing them with this command:
 sudo apt-get install git g++ cmake libboost-all-dev python libreadline-dev
 ```
 
-Note that there is no guarantee that your system lacks some required packages which are not listed here! CMake will
-inform you about missing dependencies during the build process.
+Note that there is no guarantee that your system does not lack some required packages which are not listed here!
+CMake will inform you about missing dependencies during the build process.
 
 Check out the git project (and all of its submodules) using the following command:
 
@@ -54,32 +54,36 @@ git clone https://github.com/marcelwa/fiction.git --recursive
 Several third-party libraries will be cloned within the `libs/` folder. The `cmake` build process will take care of
 them automatically.
 
+Should you have cloned the repository before, `git submodule update --init --recursive` will fetch the latest version of
+all external modules used.
+
 Afterwards, *fiction* is ready to be built. Simply enter the following commands:
 
 ```sh
 cd fiction
 mkdir build
 cd build
-cmake -DCMAKE_BUILD_TYPE=Release ..
-make -j4
+cmake ..
+make
 ```
 
-Note that this process may take a while!
+This process may take a while!
 
 You have the choice to change the `cmake` call to `cmake -DCMAKE_BUILD_TYPE=Debug ..` if you prefer building with debug
-information. Note that this will have a significant negative impact on the runtime.
+information. The build mode can also be toggled via the `ccmake` CLI. Note that building with debug information will
+have a significant negative impact on the runtime.
 
 ### Troubleshooting
 
-On some older CMake systems, it might be necessary to type
+On some CMake systems, it might be necessary to type
 
 ```sh
-make z3 -j4
-make -j4
+make z3
+make fiction
 ```
 
-after the `cmake` call to guarantee the correct order of build steps. Try this if the initial call leads to some kind
-of error messages revolving around Z3.
+after the `cmake` call instead of just `make` to guarantee the correct order of build steps. Try this if the initial
+call leads to some kind of error messages revolving around Z3.
 
 ## Usage
 
@@ -89,6 +93,8 @@ following. To get some information about the available commands, run `fiction` w
 ```sh
 ./fiction --help
 ```
+Starting the interactive mode by entering `./fiction` greets the user with a prompt. Again, input of `help` produces a
+list of available commands. You can generate a plain text documentation by entering `help --docs <filename>`. 
 
 ### Preface
 
@@ -108,9 +114,8 @@ netlists in the `benchmarks` folder.
 
 ### Stores
 
-Starting the interactive mode by entering `./fiction` greets the user with a prompt. Again, input of `help` produces a
-list of available commands. Enter `read_verilog <filename>` to read a logic network into a store. The content of the
-logic network store can be briefly viewed by entering `store -w` whereas `print -w` writes a
+When you are in interactive mode, enter `read_verilog <filename>` to read a logic network into a store. The content of
+the logic network store can be briefly viewed by entering `store -w` whereas `print -w` writes a
 [Graphviz](https://www.graphviz.org/) dot file of the current network to the standard output. Arbitrarily many logic
 networks can be held in store from which the latest is always the active one. Change active network with `set -w <n>`
 where you replace `<n>` by the number of the store element you want to activate.
@@ -143,9 +148,9 @@ simple textual representation can be viewed by entering `print -g`.
 To synthesize a gate layout to a cell level one, type `gate_to_cell`, where the `-l` flag indicates the gate library to
 use. Currently, only QCA-ONE is available which is the default setting. Cell layouts are also saved in stores which can
 be accessed by typing `store -c`. Due to significantly larger size of cell layouts compared to gate layouts, the
-`write -c` command to print layouts to the terminal is not implemented.
+`print -c` command to write layouts to the terminal should be used carefully.
 
-Nevertheless, use `write_qca <filename>.qca` to create a QCADesigner file for running physical simulations. 
+Nevertheless, you can use `write_qca <filename>.qca` to create a QCADesigner file for running physical simulations. 
 
 ### Automation by scripting
 
@@ -165,6 +170,8 @@ write_qca c17.qca
 which can be executed by `./fiction -ef c17_synth.fs -l c17_log.json` where statistics are to be logged in a JSON file
 called `c17_log.json`.
 
+These scripts can also be nested. Use `< script.fs` within a *fiction script* to load `script.fs` in that very position.
+
 Additionally, *fiction* can also be part of a bash script. Consider the following snippet
 
 ```sh
@@ -175,8 +182,9 @@ done
 ```
 
 where the for-loop iterates over all Verilog files in the `../benchmarks/TOY/` folder. Using the flag `-c`, a
-semicolon-separated list of commands can be entered in *fiction*. In this case, the files are to be read in a store, placed
-and routed using the `ortho` algorithm, synthesized to cell level, and written as QCA using their original file name.
+semicolon-separated list of commands can be entered in *fiction*. In this case, the files are to be read in a store,
+placed and routed using the `ortho` algorithm, synthesized to cell level, and written as QCA using their original file
+name.
 
 ## Uninstall
 

include/bidirectional_graph.h

@@ -445,10 +445,10 @@ class bidirectional_graph
      */
     vertices_t topological_sort() const noexcept
     {
-        vertices_t topoOrder;
-        boost::topological_sort(graph, std::back_inserter(topoOrder));
+        vertices_t topo_order;
+        boost::topological_sort(graph, std::back_inserter(topo_order));
 
-        return topoOrder;
+        return topo_order;
     }
 //    /**
 //     * Determines whether the stored graph is planar i.e. whether it does not contain a Kuratowski subgraph.

include/commands.h

@@ -103,14 +103,12 @@ namespace alice
             }
 
             // perform exact P&R
-            exact_pr pr{s.current(), std::move(config)};
+            exact_pr pr{std::move(s.current()), std::move(config)};
             auto result = pr.perform_place_and_route();
 
-            auto l = pr.get_layout();
-
             if (result.success)
             {
-                store<fcn_gate_layout_ptr>().extend() = pr.get_layout();
+                store<fcn_gate_layout_ptr>().extend() = std::move(pr.get_layout());
                 pr_result = result.json;
             }
             else
@@ -187,12 +185,12 @@ namespace alice
             }
 
             // perform heuristic P&R
-            orthogonal_pr pr{s.current()};
+            orthogonal_pr pr{std::move(s.current())};
             auto result = pr.perform_place_and_route();
 
             if (result.success)
             {
-                store<fcn_gate_layout_ptr>().extend() = pr.get_layout();
+                store<fcn_gate_layout_ptr>().extend() = std::move(pr.get_layout());
                 pr_result = result.json;
             }
             else
@@ -258,7 +256,7 @@ namespace alice
             try
             {
                 if (library == 0u)
-                    lib = std::make_shared<qca_one_library>(s.current());
+                    lib = std::make_shared<qca_one_library>(std::move(s.current()));
                 // else if (library == 1u)
                     // more libraries go here
                 else
@@ -276,7 +274,7 @@ namespace alice
             fcn_cell_layout_ptr fcl = nullptr;
             try
             {
-                fcl = std::make_shared<fcn_cell_layout>(lib);
+                fcl = std::make_shared<fcn_cell_layout>(std::move(lib));
             }
             catch (...)
             {
@@ -285,7 +283,7 @@ namespace alice
             }
 
             // store new layout
-            store<fcn_cell_layout_ptr>().extend() = fcl;
+            store<fcn_cell_layout_ptr>().extend() = std::move(fcl);
         }
 
     private:

include/energy_model.h

@@ -37,13 +37,13 @@ namespace energy
      */
     constexpr float INVERTER_STRAIGHT_FAST = 1.19f;
     /**
-     * Energy consumption (slow) of a curved inverter.
+     * Energy consumption (slow) of a bent inverter.
      */
-    constexpr float INVERTER_CURVED_SLOW = 0.10f;
+    constexpr float INVERTER_BENT_SLOW = 0.10f;
     /**
-     * Energy consumption (fast) of a curved inverter.
+     * Energy consumption (fast) of a bent inverter.
      */
-    constexpr float INVERTER_CURVED_FAST = 0.84f;
+    constexpr float INVERTER_BENT_FAST = 0.84f;
     /**
      * Energy consumption (slow) of a crossing.
      */

include/exact_pr.h

@@ -29,7 +29,7 @@ class exact_pr : public place_route
      * @param ln Logic network.
      * @param config Configuration object storing all the bounds, flags, and so on.
      */
-    exact_pr(std::shared_ptr<logic_network> ln, exact_pr_config&& config);
+    exact_pr(std::shared_ptr<logic_network>&& ln, exact_pr_config&& config);
     /**
      * Default Destructor.
      */

include/fcn_cell_layout.h

@@ -75,9 +75,9 @@ class fcn_cell_layout : public fcn_layout
      * Standard constructor. Creates an FCN cell layout from a gate library that is associated with a fcn_gate_layout.
      * All tiles from the stored gate layout will be mapped to cells using the library.
      *
-     * @param library FCN gate library to use for mapping operations.
+     * @param lib FCN gate library to use for mapping operations.
      */
-    fcn_cell_layout(fcn_gate_library_ptr library);
+    explicit fcn_cell_layout(fcn_gate_library_ptr&& lib);
     /**
      * Default copy constructor.
      */
@@ -210,6 +210,15 @@ class fcn_cell_layout : public fcn_layout
      * @return Name of the layout.
      */
     std::string get_name() const noexcept;
+    /**
+     * Prints the assigned cell types to the given std::ostream channel. A textual representation is used for
+     * visualization. Currently only one crossing layer can be represented correctly. This is more of a debug function
+     * and unsuitable for large layouts.
+     *
+     * @param os An std::ostream channel to write the textual representation of this layout into.
+     * @param io_color Flag to indicate features like PI/PO should be printed with color escape.
+     */
+    void write_layout(std::ostream& os = std::cout, bool io_color = true) const noexcept;
 
 private:
     /**