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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4k 594

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.2k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.3k 206

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1k 324

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 816 221

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 725 176

Repositories

Showing 10 of 109 repositories
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 114 Apache-2.0 23 16 24 Updated Oct 16, 2024
  • verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    chipsalliance/verible’s past year of commit activity
    C++ 1,348 206 469 (15 issues need help) 24 Updated Oct 16, 2024
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 248 Apache-2.0 75 20 9 Updated Oct 16, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 70 Apache-2.0 41 89 57 Updated Oct 16, 2024
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,952 Apache-2.0 594 309 (1 issue needs help) 160 Updated Oct 16, 2024
  • synlig Public

    SystemVerilog support for Yosys

    chipsalliance/synlig’s past year of commit activity
    Verilog 160 Apache-2.0 21 63 8 Updated Oct 16, 2024
  • chisel-nix Public

    Nix template for the chisel-based industrial designing flows.

    chipsalliance/chisel-nix’s past year of commit activity
    Nix 27 1 0 0 Updated Oct 16, 2024
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Oct 16, 2024
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 289 ISC 75 45 (5 issues need help) 22 Updated Oct 15, 2024
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    chipsalliance/Caliptra’s past year of commit activity
    138 Apache-2.0 30 15 6 Updated Oct 15, 2024
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