feature request: strength reduction for division or remainder when the denominator is a constant power of two

[ekiwi]

Feature Description

If there is a division or a remainder operation where the denominator is a constant power of two, the firrtl compiler should replace the div/rem operation with appropriate bit slicing or a static shift. Personally I would prefer to just use bit slicing since that is imho a better canonical form.

This would allow users to write:

val r = in / 4.U

instead of:

val r = in >> 2.U

and get (almost) identical Verilog.

This is important because a division in Verilog might be a red flag. But also, personally, I would prefer if the SMT/btor2 backend only emitted div/rem is it absolutely needs to.

Type of Feature

• better optimization