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RX DMA works
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Comma Device committed Sep 3, 2024
1 parent 68ce72f commit fae57cb
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Showing 5 changed files with 31 additions and 17 deletions.
4 changes: 2 additions & 2 deletions board/boards/cuatro.h
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Original file line number Diff line number Diff line change
Expand Up @@ -127,8 +127,8 @@ void cuatro_init(void) {
set_gpio_alternate(GPIOC, 0, GPIO_AF8_SAI4); // SAI4_FS_B
set_gpio_alternate(GPIOD, 11, GPIO_AF10_SAI4); // SAI4_SD_A
set_gpio_alternate(GPIOE, 3, GPIO_AF8_SAI4); // SAI4_SD_B
set_gpio_alternate(GPIOE, 4, GPIO_AF10_SAI4); // SAI4_D2
set_gpio_alternate(GPIOE, 5, GPIO_AF10_SAI4); // SAI4_CK2
set_gpio_alternate(GPIOE, 4, GPIO_AF10_SAI4); // SAI4_D2
set_gpio_alternate(GPIOE, 5, GPIO_AF10_SAI4); // SAI4_CK2
set_gpio_alternate(GPIOE, 6, GPIO_AF10_SAI4); // SAI4_MCLK_B
sound_init();
}
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2 changes: 1 addition & 1 deletion board/config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
//#define DEBUG_UART
//#define DEBUG_USB
//#define DEBUG_SPI
//#define DEBUG_FAULTS
#define DEBUG_FAULTS
//#define DEBUG_COMMS
//#define DEBUG_FAN

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31 changes: 20 additions & 11 deletions board/drivers/sound.h
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@@ -1,17 +1,17 @@

const uint8_t sine[360] = { 127U, 129U, 131U, 133U, 135U, 138U, 140U, 142U, 144U, 146U, 149U, 151U, 153U, 155U, 157U, 159U, 161U, 164U, 166U, 168U, 170U, 172U, 174U, 176U, 178U, 180U, 182U, 184U, 186U, 188U, 190U, 192U, 194U, 196U, 197U, 199U, 201U, 203U, 205U, 206U, 208U, 210U, 211U, 213U, 215U, 216U, 218U, 219U, 221U, 222U, 224U, 225U, 227U, 228U, 229U, 230U, 232U, 233U, 234U, 235U, 236U, 238U, 239U, 240U, 241U, 242U, 242U, 243U, 244U, 245U, 246U, 247U, 247U, 248U, 249U, 249U, 250U, 250U, 251U, 251U, 252U, 252U, 252U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 252U, 252U, 252U, 251U, 251U, 250U, 250U, 249U, 249U, 248U, 247U, 247U, 246U, 245U, 244U, 243U, 243U, 242U, 241U, 240U, 239U, 238U, 237U, 235U, 234U, 233U, 232U, 231U, 229U, 228U, 227U, 225U, 224U, 222U, 221U, 219U, 218U, 216U, 215U, 213U, 212U, 210U, 208U, 207U, 205U, 203U, 201U, 199U, 198U, 196U, 194U, 192U, 190U, 188U, 186U, 184U, 182U, 180U, 178U, 176U, 174U, 172U, 170U, 168U, 166U, 164U, 162U, 160U, 157U, 155U, 153U, 151U, 149U, 147U, 144U, 142U, 140U, 138U, 136U, 133U, 131U, 129U, 127U, 124U, 122U, 120U, 118U, 116U, 113U, 111U, 109U, 107U, 105U, 102U, 100U, 98U, 96U, 94U, 92U, 90U, 87U, 85U, 83U, 81U, 79U, 77U, 75U, 73U, 71U, 69U, 67U, 65U, 63U, 61U, 59U, 58U, 56U, 54U, 52U, 50U, 49U, 47U, 45U, 43U, 42U, 40U, 38U, 37U, 35U, 34U, 32U, 31U, 29U, 28U, 27U, 25U, 24U, 23U, 21U, 20U, 19U, 18U, 17U, 16U, 14U, 13U, 12U, 12U, 11U, 10U, 9U, 8U, 7U, 7U, 6U, 5U, 4U, 4U, 3U, 3U, 2U, 2U, 1U, 1U, 1U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 1U, 1U, 2U, 2U, 3U, 3U, 4U, 4U, 5U, 6U, 6U, 7U, 8U, 9U, 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U, 17U, 19U, 20U, 21U, 22U, 24U, 25U, 26U, 28U, 29U, 30U, 32U, 33U, 35U, 36U, 38U, 40U, 41U, 43U, 45U, 46U, 48U, 50U, 52U, 53U, 55U, 57U, 59U, 61U, 63U, 65U, 67U, 69U, 70U, 72U, 74U, 77U, 79U, 81U, 83U, 85U, 87U, 89U, 91U, 93U, 95U, 98U, 100U, 102U, 104U, 106U, 108U, 111U, 113U, 115U, 117U, 119U, 122U, 124U };

// 16bit, 48kHz, stereo, 0.1s buffers
#define RX_BUF_SIZE 9600U
// 16bit, 48kHz, stereo, 0.04s buffers
#define RX_BUF_SIZE 2000U
struct sound_buf_t {
uint16_t buf[RX_BUF_SIZE];
} sound_buf_t;

struct sound_buf_t rx_buf[2];
__attribute__((section(".sram4"))) struct sound_buf_t rx_buf[2];

void BDMA_Channel0_IRQ_Handler(void) {
// clear flag
BDMA->IFCR = BDMA_IFCR_CTCIF0;
BDMA->IFCR |= BDMA_IFCR_CGIF0;

print("sound dma interrupt\n");
}
Expand All @@ -21,7 +21,7 @@ void sai4_init(void) {

// stereo audio in (needs to be combined in fw, or set to mono on the host side)
register_set(&SAI4_Block_B->CR1, SAI_xCR1_DMAEN | (0b00 << SAI_xCR1_SYNCEN_Pos) | (0b100 << SAI_xCR1_DS_Pos) | (0b11 << SAI_xCR1_MODE_Pos), 0x0FFB3FEFU);
register_set(&SAI4_Block_B->CR2, 0U, 0xFFFBU); // TODO: mute detection
register_set(&SAI4_Block_B->CR2, (0b001 << SAI_xCR2_FTH_Pos), 0xFFFBU); // TODO: mute detection
register_set(&SAI4_Block_B->FRCR, (31U << SAI_xFRCR_FRL_Pos), 0x7FFFFU);
register_set(&SAI4_Block_B->SLOTR, (0b11 << SAI_xSLOTR_SLOTEN_Pos) | (1U << SAI_xSLOTR_NBSLOT_Pos) | (0b01 << SAI_xSLOTR_SLOTSZ_Pos), 0xFFFF0FDFU); // NBSLOT definition is vague

Expand All @@ -33,14 +33,22 @@ void sai4_init(void) {
register_set(&SAI4->PDMCR, (0b1 << SAI_PDMCR_CKEN2_Pos) | (0b00 << SAI_PDMCR_MICNBR_Pos) | (0b1 << SAI_PDMCR_PDMEN_Pos), 0x331);

// init DMA (SAI4_B -> memory, double buffers)
register_set(&BDMA_Channel0->CPAR, (uint32_t) &SAI4_Block_B->DR, 0xFFFFFFFFU);
register_set(&BDMA_Channel0->CM0AR, (uint32_t) &rx_buf[0].buf, 0xFFFFFFFFU);
register_set(&BDMA_Channel0->CM1AR, (uint32_t) &rx_buf[1].buf, 0xFFFFFFFFU);
register_set(&BDMA_Channel0->CNDTR, RX_BUF_SIZE, 0xFFFFU);
register_set(&BDMA_Channel0->CCR, BDMA_CCR_DBM | (0b01 << BDMA_CCR_MSIZE_Pos) | (0b01 << BDMA_CCR_PSIZE_Pos) | BDMA_CCR_MINC | BDMA_CCR_CIRC | BDMA_CCR_TCIE, 0x1FFFFU);
register_set(&BDMA_Channel0->CPAR, (uint32_t) &(SAI4_Block_B->DR), 0xFFFFFFFFU);
register_set(&BDMA_Channel0->CM0AR, (uint32_t) rx_buf[0].buf, 0xFFFFFFFFU);
register_set(&BDMA_Channel0->CM1AR, (uint32_t) rx_buf[1].buf, 0xFFFFFFFFU);
BDMA_Channel0->CNDTR = RX_BUF_SIZE;
register_set(&BDMA_Channel0->CCR, BDMA_CCR_DBM | (0b01 << BDMA_CCR_MSIZE_Pos) | (0b01 << BDMA_CCR_PSIZE_Pos) | BDMA_CCR_MINC | BDMA_CCR_CIRC | BDMA_CCR_TCIE, 0xFFFFU);
register_set(&DMAMUX2_Channel0->CCR, 16U, DMAMUX_CxCR_DMAREQ_ID_Msk); // SAI4_B_DMA
register_set_bits(&BDMA_Channel0->CCR, BDMA_CCR_EN);

// register_set(&BDMA_Channel0->CPAR, (uint32_t) &(SAI4_Block_B->DR), 0xFFFFFFFFU);
// register_set(&BDMA_Channel0->CM0AR, (uint32_t) rx_buf[0].buf, 0xFFFFFFFFU);
// BDMA_Channel0->CNDTR = RX_BUF_SIZE;
// //register_set(&BDMA_Channel0->CCR, BDMA_CCR_DBM | (0b01 << BDMA_CCR_MSIZE_Pos) | (0b01 << BDMA_CCR_PSIZE_Pos) | BDMA_CCR_MINC | BDMA_CCR_CIRC | BDMA_CCR_TCIE, 0xFFFFU);
// register_set(&BDMA_Channel0->CCR, (0b01 << BDMA_CCR_MSIZE_Pos) | (0b01 << BDMA_CCR_PSIZE_Pos) | BDMA_CCR_MINC | BDMA_CCR_TCIE, 0xFFFFU);
// register_set(&DMAMUX2_Channel0->CCR, 16U, DMAMUX_CxCR_DMAREQ_ID_Msk); // SAI4_B_DMA
// register_set_bits(&BDMA_Channel0->CCR, BDMA_CCR_EN);

// enable all initted blocks
register_set_bits(&SAI4_Block_A->CR1, SAI_xCR1_SAIEN);
register_set_bits(&SAI4_Block_B->CR1, SAI_xCR1_SAIEN);
Expand Down Expand Up @@ -73,6 +81,7 @@ void sound_init(void) {
// TIM7->CR1 |= TIM_CR1_CEN;

REGISTER_INTERRUPT(BDMA_Channel0_IRQn, BDMA_Channel0_IRQ_Handler, 20U, FAULT_INTERRUPT_RATE_SOUND_DMA)

sai4_init();
NVIC_EnableIRQ(BDMA_Channel0_IRQn);

}
8 changes: 6 additions & 2 deletions board/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -167,8 +167,12 @@ void tick_handler(void) {
}

#ifdef STM32H7
while((SAI4_Block_A->SR & SAI_xSR_FLVL) != 0U) {
puth4(SAI4_Block_A->DR); print("\n");
// while((SAI4_Block_B->SR & SAI_xSR_FLVL) != 0U) {
// puth4(SAI4_Block_B->DR); print("\n");
// }

if(rx_buf[0].buf[0] != 0U) {
print("RX BUFS[0]: "); puth4(rx_buf[0].buf[0]); print(" "); puth4(rx_buf[1].buf[0]); print("\n");
}
#endif

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3 changes: 2 additions & 1 deletion board/stm32h7/peripherals.h
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Original file line number Diff line number Diff line change
Expand Up @@ -97,13 +97,14 @@ void peripherals_init(void) {
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOFEN;
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOGEN;

// Enable CPU access to SRAM1 and SRAM2 (in domain D2) for DMA
// Enable CPU access to SRAMs for DMA
RCC->AHB2ENR |= RCC_AHB2ENR_SRAM1EN | RCC_AHB2ENR_SRAM2EN;

// Supplemental
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; // DAC DMA
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; // SPI DMA
RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;
RCC->AHB4ENR |= RCC_AHB4ENR_BDMAEN; // Audio DMA

// Connectivity
RCC->APB2ENR |= RCC_APB2ENR_SPI4EN; // SPI
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