Fix Seq Mem Ports

file-tests/should-futil/fixed-point-multi-cycle.expect

@@ -38,10 +38,11 @@ component main() -> () {
       mult_pipe1.go = !mult_pipe1.done ? 1'd1;
     }
     group upd0<"promotable"=1> {
+      d0.content_en = 1'd1;
       d0.addr0 = const0.out;
       d0.write_en = 1'd1;
       d0.write_data = bin_read1_0.out;
-      upd0[done] = d0.write_done;
+      upd0[done] = d0.done;
     }
   }
   control {

file-tests/should-futil/for-multi-dim.expect

@@ -42,20 +42,21 @@ component main() -> () {
     }
     group let2<"promotable"=2> {
       A_read0_0.in = A.read_data;
-      A_read0_0.write_en = A.read_done;
+      A_read0_0.write_en = A.done;
       let2[done] = A_read0_0.done;
+      A.content_en = 1'd1;
       A.addr1 = j0.out;
       A.addr0 = i0.out;
-      A.read_en = 1'd1;
     }
     group upd0<"promotable"=1> {
+      B.content_en = 1'd1;
       B.addr1 = j0.out;
       B.addr0 = i0.out;
       B.write_en = 1'd1;
       add0.left = A_read0_0.out;
       add0.right = const4.out;
       B.write_data = add0.out;
-      upd0[done] = B.write_done;
+      upd0[done] = B.done;
     }
     group upd1<"promotable"=1> {
       j0.write_en = 1'd1;

file-tests/should-futil/for.expect

@@ -27,18 +27,19 @@ component main() -> () {
     }
     group let1<"promotable"=2> {
       A_read0_0.in = A.read_data;
-      A_read0_0.write_en = A.read_done;
+      A_read0_0.write_en = A.done;
       let1[done] = A_read0_0.done;
+      A.content_en = 1'd1;
       A.addr0 = i0.out;
-      A.read_en = 1'd1;
     }
     group upd0<"promotable"=1> {
+      B.content_en = 1'd1;
       B.addr0 = i0.out;
       B.write_en = 1'd1;
       add0.left = A_read0_0.out;
       add0.right = const2.out;
       B.write_data = add0.out;
-      upd0[done] = B.write_done;
+      upd0[done] = B.done;
     }
     group upd1<"promotable"=1> {
       i0.write_en = 1'd1;

file-tests/should-futil/invoke-with-memories.expect

@@ -17,16 +17,17 @@ component mem_copy() -> () {
     }
     group let1<"promotable"=2> {
       src_read0_0.in = src.read_data;
-      src_read0_0.write_en = src.read_done;
+      src_read0_0.write_en = src.done;
       let1[done] = src_read0_0.done;
+      src.content_en = 1'd1;
       src.addr0 = zero_0.out;
-      src.read_en = 1'd1;
     }
     group upd0<"promotable"=1> {
+      dest.content_en = 1'd1;
       dest.addr0 = zero_0.out;
       dest.write_en = 1'd1;
       dest.write_data = src_read0_0.out;
-      upd0[done] = dest.write_done;
+      upd0[done] = dest.done;
     }
   }
   control {

file-tests/should-futil/use-plus-equals.expect

@@ -47,20 +47,21 @@ component use_plus_equals() -> () {
     }
     group let3<"promotable"=2> {
       red_read00.in = x2.read_data;
-      red_read00.write_en = x2.read_done;
+      red_read00.write_en = x2.done;
       let3[done] = red_read00.done;
+      x2.content_en = 1'd1;
       x2.addr1 = __j0.out;
       x2.addr0 = __i0.out;
-      x2.read_en = 1'd1;
     }
     group upd0<"promotable"=1> {
+      x2.content_en = 1'd1;
       x2.addr1 = __j0.out;
       x2.addr0 = __i0.out;
       x2.write_en = 1'd1;
       add0.left = red_read00.out;
       add0.right = __x_0.out;
       x2.write_data = add0.out;
-      upd0[done] = x2.write_done;
+      upd0[done] = x2.done;
     }
     group upd1<"promotable"=1> {
       __j0.write_en = 1'd1;