Merge pull request #2 from wengwz/main

add support for two computation modes and reconstruct codes

.gitignore

@@ -6,6 +6,8 @@ output/
 *.log
 *.jou
 *.txt
+*.mem
 __pycache__
 logs/
-gen/
+gen/
+verilog/

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "lib/blue-wrapper"]
+	path = lib/blue-wrapper
+	url = https://github.com/wengwz/blue-wrapper.git

backend/vivado/Makefile

@@ -1,74 +1,69 @@
-PWD = $(shell pwd)
-BUILDDIR = build
-SRCDIR = ../../src
-VLOGDIR = generated
+ROOT_DIR = $(abspath ../../)
+SCRIPTS_DIR = $(ROOT_DIR)/scripts
+include $(SCRIPTS_DIR)/Makefile.base
+LOCALSRCDIR = $(ROOT_DIR)/src
+LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src
+
+
+FILE = CrcAxiStreamCustom.bsv
+TOPMODULE = mkCrcRawAxiStreamCustom
+TABDIR = .
+VLOGDIR = verilog
+VLOGFILE = $(VLOGDIR)/$(TOPMODULE).v
+LIST_VERILOG_TCL = $(SCRIPTS_DIR)/listVlogFiles.tcl
+
+# CRC Configurations
+JSON_CONF_FILE = $(SCRIPTS_DIR)/config/crc_32_256_recv.json
+CRC_WIDTH = 32
+AXI_KEEP_WIDTH = 32
+POLY = 79764919
+INIT_VAL = 4294967295
+FINAL_XOR = 4294967295
+REV_INPUT = BIT_ORDER_REVERSE
+REV_OUTPUT = BIT_ORDER_REVERSE
+MEM_FILE_PREFIX = crc_tab
+CRC_MODE = CRC_MODE_RECV
+
+MACROFLAGS = -D CRC_WIDTH=$(CRC_WIDTH) \
+			 -D AXI_KEEP_WIDTH=$(AXI_KEEP_WIDTH) \
+			 -D POLY=$(POLY) \
+			 -D INIT_VAL=$(INIT_VAL) \
+			 -D FINAL_XOR=$(FINAL_XOR) \
+			 -D REV_INPUT=$(REV_INPUT) \
+			 -D REV_OUTPUT=$(REV_OUTPUT) \
+			 -D MEM_FILE_PREFIX="\"$(MEM_FILE_PREFIX)\"" \
+			 -D CRC_MODE=$(CRC_MODE)
+
+# vivado config
+XDCDIR = $(shell pwd)
 OUTPUTDIR = output
+SUB_OUTPUTDIR = 
 ONLYSYNTH = 0
 CLK = main_clock
-GEN_TAB = $(SRCDIR)/gen_crc_tab.py
-LIST_VLOG = ../../scripts/listVlogFiles.tcl
-
-CRC_WIDTH ?= 8
-AXI_WIDTH ?= 64
-TARGET = Crc$(CRC_WIDTH)AxiStream$(AXI_WIDTH)
-TARGETFILE = $(SRCDIR)/Crc$(CRC_WIDTH)AxiStream.bsv
-TOPMODULE = mk$(TARGET)
-
-SUB_VLOGDIR = $(VLOGDIR)/$(TARGET)
-SUB_OUTPUTDIR = $(OUTPUTDIR)/$(TARGET)
 
 export TOP = $(TOPMODULE)
-export RTL = $(SUB_VLOGDIR)
-export XDC = $(PWD)
-export OUTPUT = $(SUB_OUTPUTDIR)
+export RTL = $(VLOGDIR)
+export XDC = $(XDCDIR)
+export OUTPUT = $(OUTPUTDIR)/$(SUB_OUTPUTDIR)
 export SYNTHONLY = $(ONLYSYNTH)
 export CLOCKS = $(CLK)
 
-TRANSFLAGS = -aggressive-conditions # -lift -split-if
-RECOMPILEFLAGS = -u -show-compiles
-SCHEDFLAGS = -show-schedule -sched-dot # -show-rule-rel dMemInit_request_put doExecute
-#	-show-elab-progress
-DEBUGFLAGS = -check-assert \
-	-continue-after-errors \
-	-keep-fires \
-	-keep-inlined-boundaries \
-	-show-method-bvi \
-	-show-method-conf \
-	-show-module-use \
-	-show-range-conflict \
-	-show-stats \
-	-warn-action-shadowing \
-	-warn-method-urgency \
-#	-promote-warnings ALL
-VERILOGFLAGS = -verilog -remove-dollar -remove-unused-modules # -use-dpi -verilog-filter cmd
-BLUESIMFLAGS = -parallel-sim-link 16 # -systemc
-OUTDIR = -bdir $(BUILDDIR) -info-dir $(BUILDDIR) -simdir $(BUILDDIR) -vdir $(BUILDDIR)
-WORKDIR = -fdir $(abspath .)
-BSVSRCDIR = -p +:$(abspath $(SRCDIR))
-DIRFLAGS = $(BSVSRCDIR) $(OUTDIR) $(WORKDIR)
-MISCFLAGS = -print-flags -show-timestamps -show-version # -steps 1000000000000000 -D macro
-RUNTIMEFLAGS = +RTS -K256M -RTS
-SIMEXE = $(BUILDDIR)/out
+table:
+	mkdir -p $(TABDIR)
+	python3 $(SCRIPTS_DIR)/gen_crc_tab.py $(JSON_CONF_FILE) $(TABDIR)
 
-compile:
+verilog: table
 	mkdir -p $(BUILDDIR)
-	bsc -elab -sim -verbose $(BLUESIMFLAGS) $(DEBUGFLAGS) $(DIRFLAGS) $(MISCFLAGS) $(RECOMPILEFLAGS) $(RUNTIMEFLAGS) $(SCHEDFLAGS) $(TRANSFLAGS) -g $(TOPMODULE) $(TARGETFILE)
-
-link: compile
-	bsc -sim $(BLUESIMFLAGS) $(DIRFLAGS) $(RECOMPILEFLAGS) $(SCHEDFLAGS) $(TRANSFLAGS) -e $(TOPMODULE) -o $(SIMEXE)
-
-
-verilog: link
-	bsc $(VERILOGFLAGS) $(DIRFLAGS) $(RECOMPILEFLAGS) $(TRANSFLAGS) -g $(TOPMODULE) $(TARGETFILE)
-	mkdir -p $(SUB_VLOGDIR)
-	bluetcl $(LIST_VLOG) -bdir $(BUILDDIR) -vdir $(BUILDDIR) $(TOPMODULE) $(TOPMODULE) | grep -i '\.v' | xargs -I {} cp {} $(SUB_VLOGDIR)
-	python3 $(GEN_TAB) $(CRC_WIDTH) $(AXI_WIDTH)
+	bsc -elab $(VERILOGFLAGS) $(DIRFLAGS) $(MISCFLAGS) $(RECOMPILEFLAGS) $(RUNTIMEFLAGS) $(TRANSFLAGS) $(MACROFLAGS) -g $(TOPMODULE) $(LOCALSRCDIR)/$(FILE)
+	mkdir -p $(VLOGDIR)
+	echo "" > $(VLOGFILE)
+	bluetcl $(LIST_VERILOG_TCL) -bdir $(BUILDDIR) -vdir $(BUILDDIR) $(TOPMODULE) $(TOPMODULE) | grep -i '\.v' | xargs -I {} cat {} >> $(VLOGFILE)
 
 vivado: verilog
 	vivado -mode batch -source non_project_build.tcl 2>&1 | tee ./run.log
 
 clean:
 	rm -rf $(BUILDDIR) $(VLOGDIR) $(OUTPUTDIR) .Xil *.jou *.log *.mem
 
-.PHONY: compile link clean vivado
-.DEFAULT_GOAL := vivado
+.PHONY: table compile verilog clean vivado
+.DEFAULT_GOAL := vivado

backend/vivado/run_vivado.py

@@ -0,0 +1,67 @@
+import os
+import sys
+import json
+from functools import reduce
+
+
+def run_vivado(conf_file_path):
+    with open(conf_file_path) as json_file:
+        crc_config = json.load(json_file)
+
+    crc_width = crc_config["crc_width"]
+    axi_keep_width = crc_config["axi_keep_width"]
+    polynomial = int(crc_config["polynomial"], 16)
+    init_value = int(crc_config["init_value"], 16)
+    final_xor = int(crc_config["final_xor"], 16)
+    reverse_input = crc_config["reverse_input"]
+
+    if reverse_input:
+        reverse_input = "BIT_ORDER_REVERSE"
+    else:
+        reverse_input = "BIT_ORDER_NOT_REVERSE"
+
+    reverse_output = crc_config["reverse_output"]
+    if reverse_output:
+        reverse_output = "BIT_ORDER_REVERSE"
+    else:
+        reverse_output = "BIT_ORDER_NOT_REVERSE"
+
+    mem_file_prefix = crc_config["mem_file_prefix"]
+    crc_mode = crc_config["crc_mode"]
+    conf_file_prefix = os.path.basename(conf_file_path)
+    conf_file_prefix = os.path.splitext(conf_file_prefix)[0]
+    print(
+        f"Run Vivado on: crc_width={crc_width} axi_keep_width={axi_keep_width} crc_mode={crc_mode}"
+    )
+
+    macros = [f"JSON_CONF_FILE={conf_file_path}"]
+    macros.append(f"CRC_WIDTH={crc_width}")
+    macros.append(f"AXI_KEEP_WIDTH={axi_keep_width}")
+    macros.append(f"POLY={polynomial}")
+    macros.append(f"INIT_VAL={init_value}")
+    macros.append(f"FINAL_XOR={final_xor}")
+    macros.append(f"REV_INPUT={reverse_input}")
+    macros.append(f"REV_OUTPUT={reverse_output}")
+    macros.append(f"MEM_FILE_PREFIX={mem_file_prefix}")
+    macros.append(f"CRC_MODE={crc_mode}")
+    macros.append(f"SUB_OUTPUTDIR={conf_file_prefix}")
+
+    make_args = reduce(lambda x, y: x + " " + y, macros)
+    os.system("rm -rf build verilog *.mem")
+    result = os.system(f"make {make_args}")
+    return result
+
+
+if __name__ == "__main__":
+    if len(sys.argv) == 2:
+        conf_file_path = sys.argv[1]
+        conf_file_path = os.path.abspath(conf_file_path)
+        run_vivado(conf_file_path)
+    else:
+        config_dir = os.path.abspath("../../scripts/config")
+        for root, dirs, files in os.walk(config_dir):
+            for file_name in files:
+                conf_file_path = os.path.join(root, file_name)
+                result = run_vivado(conf_file_path)
+                info = f"Run Vivado Failed on the configuration of {file_name}."
+                assert result == 0, info

run.sh

@@ -18,12 +18,7 @@ COCOTB_DIR=${TEST_DIR}/cocotb
 echo -e "\nStart formatting Codes"
 black --check $(find ./ -name "*.py")
 
-# Run Bluesim Tests
-echo -e "\nStart Bluesim Tests"
-cd ${BLUESIM_DIR}
-source ./run_tests.sh
-
 # Run Cocotb Tests
-echo -e "\nStart Cocotb Tests"
+echo -e "\nStart Cocotb Testbenches"
 cd ${COCOTB_DIR}
-source ./run_tests.sh
+python3 run_tests.py