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Merge pull request #146 from davidgiven/sixbit
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Switch to a simplified encoding with a six-bit timer.
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@davidgiven
davidgiven authored Apr 2, 2020
2 parents e6da85b + 1509e1f commit deaab94
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Showing 31 changed files with 599 additions and 993 deletions.
628 changes: 314 additions & 314 deletions FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
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14 changes: 0 additions & 14 deletions FluxEngine.cydsn/FluxEngine.cyprj
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Original file line number Diff line number Diff line change
Expand Up @@ -39,20 +39,6 @@
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<build_action v="SOURCE_C;;;;" />
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90 changes: 39 additions & 51 deletions FluxEngine.cydsn/Sampler/Sampler.v
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Expand Up @@ -19,90 +19,78 @@ module Sampler (

//`#start body` -- edit after this line, do not edit this line

localparam STATE_RESET = 0;
localparam STATE_WAITING = 1;
localparam STATE_OPCODE = 2;
localparam STATE_WAITING = 0;
localparam STATE_OPCODE = 1;

reg [1:0] state;
reg [6:0] counter;
reg [0:0] state;
reg [5:0] counter;

reg oldsampleclock;
wire sampleclocked;
assign sampleclocked = !oldsampleclock && sampleclock;

reg oldindex;
wire indexed;
assign indexed = !oldindex && index;

wire rdataed;
reg oldrdata;
assign rdataed = !oldrdata && rdata;

reg sampleclocked;
reg indexed;
reg rdataed;

assign req = (state == STATE_OPCODE);

always @(posedge clock)
begin
if (reset)
begin
state <= STATE_RESET;
state <= STATE_WAITING;
opcode <= 0;
sampleclocked <= 0;
indexed <= 0;
rdataed <= 0;
oldsampleclock <= 0;
oldindex <= 0;
oldrdata <= 0;
counter <= 0;
end
else
begin
/* Remember positive egdes for sampleclock, index and rdata. */

if (sampleclock && !oldsampleclock)
sampleclocked <= 1;
oldsampleclock <= sampleclock;

if (index && !oldindex)
indexed <= 1;
oldindex <= index;

if (rdata && !oldrdata)
rdataed <= 1;
oldrdata <= rdata;

case (state)
STATE_RESET:
state <= STATE_WAITING;

STATE_WAITING:
begin
/* If something has happened, emit any necessary interval byte. */
if ((rdataed || indexed) && (counter != 0))
if (sampleclocked)
begin
opcode <= {0, counter};
state <= STATE_OPCODE;
end
else if (indexed)
begin
oldindex <= 1;
opcode <= 8'h81;
state <= STATE_OPCODE;
end
else if (rdataed)
begin
oldrdata <= 1;
opcode <= 8'h80;
state <= STATE_OPCODE;
end
else if (sampleclocked)
begin
oldsampleclock <= 1;
if (counter == 7'h7f)
if (rdataed || indexed || (counter == 6'h3f))
begin
opcode <= {0, counter};
opcode <= {rdataed, indexed, counter};
rdataed <= 0;
indexed <= 0;
counter <= 0;
state <= STATE_OPCODE;
end
counter <= counter + 1;
else
counter <= counter + 1;

sampleclocked <= 0;
end

/* Reset state once we've done the thing. */

if (oldrdata && !rdata)
oldrdata <= 0;
if (oldindex && !index)
oldindex <= 0;
if (oldsampleclock && !sampleclock)
oldsampleclock <= 0;
end

STATE_OPCODE: /* opcode or interval byte sent here */
STATE_OPCODE: /* opcode sent here */
begin
state <= STATE_WAITING;
counter <= 0;
end
endcase
end
end

//`#end` -- edit above this line, do not edit this line
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62 changes: 24 additions & 38 deletions FluxEngine.cydsn/Sequencer/Sequencer.v
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Original file line number Diff line number Diff line change
Expand Up @@ -19,19 +19,15 @@ module Sequencer (
//`#start body` -- edit after this line, do not edit this line

localparam STATE_LOAD = 0;
localparam STATE_WAITING = 1;
localparam STATE_PULSING = 2;
localparam STATE_INDEXING = 3;
localparam STATE_WRITING = 1;

localparam OPCODE_PULSE = 8'h80;
localparam OPCODE_INDEX = 8'h81;

reg [1:0] state;
reg [6:0] countdown;
reg state;
reg [5:0] countdown;
reg pulsepending;

assign req = (!reset && (state == STATE_LOAD));
assign wdata = (state == STATE_PULSING);
assign debug_state = state;
assign wdata = (!reset && (state == STATE_WRITING) && (countdown == 0) && pulsepending);
assign debug_state = 0;

reg olddataclock;
wire dataclocked;
Expand All @@ -52,49 +48,39 @@ begin
begin
state <= STATE_LOAD;
countdown <= 0;
pulsepending <= 0;
oldsampleclock <= 0;
end
else
begin
if (!oldsampleclock && sampleclock)
sampleclocked <= 1;
oldsampleclock <= sampleclock;

case (state)
STATE_LOAD:
/* Wait for a posedge on dataclocked, indicating an opcode has
begin
/* A posedge on dataclocked indicates that another opcode has
* arrived. */
if (dataclocked)
case (opcode)
OPCODE_PULSE:
state <= STATE_PULSING;

OPCODE_INDEX:
state <= STATE_INDEXING;

default:
begin
countdown <= opcode[6:0];
state <= STATE_WAITING;
end
endcase
begin
pulsepending <= opcode[7];
countdown <= opcode[5:0];
state <= STATE_WRITING;
end
end

STATE_WAITING:
STATE_WRITING:
begin
if (sampleclocked)
begin
sampleclocked <= 0;
countdown <= countdown - 1;
/* Nasty fudge factor here to account for one to two
* sample ticks lost per pulse. */
if (countdown <= 2)
if (countdown == 0)
state <= STATE_LOAD;
else
countdown <= countdown - 1;
sampleclocked <= 0;
end

STATE_PULSING:
state <= STATE_LOAD;

STATE_INDEXING:
if (indexed)
state <= STATE_LOAD;
end
endcase
end
end
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