build/microsemi/libero_soc.py: replaced tabs by spaces

litex/build/microsemi/libero_soc.py

@@ -98,7 +98,7 @@ def build_project(self):
             "-use_enhanced_constraint_flow 1",
             "-hdl {VERILOG}",
             "-family {PolarFire}",
-	        "-die {}".format(self.tcl_name(die)),
+            "-die {}".format(self.tcl_name(die)),
             "-package {}".format(self.tcl_name(package)),
             "-speed {}".format(self.tcl_name("-" + speed)),
             "-die_voltage {1.0}",
@@ -115,16 +115,16 @@ def build_project(self):
             filename_tcl = "{" + filename + "}"
             tcl.append("import_files -hdl_source " + filename_tcl)
 
-	# Building the design Hierarchy
+        # Building the design Hierarchy
         tcl.append("build_design_hierarchy")
         # Set top level
         tcl.append("set_root -module {}".format(self.tcl_name(self._build_name + "::work")))
 
         # Copy init files FIXME: support for include path on LiberoSoC?
         # Commenting out copy init file as this breaks the LiberoSoC flow.
-#        for file in os.listdir(self._build_dir):
-#            if file.endswith(".init"):
-#                tcl.append("file copy -- {} impl/synthesis".format(file))
+        #for file in os.listdir(self._build_dir):
+        #    if file.endswith(".init"):
+        #        tcl.append("file copy -- {} impl/synthesis".format(file))
 
         # Import io constraints
         tcl.append("import_files -io_pdc {}".format(self.tcl_name(self._build_name + "_io.pdc")))
@@ -211,7 +211,7 @@ def build_timing_constraints(self, vns):
         return (self._build_name + ".sdc", "SDC")
 
     # Script ---------------------------------------------------------------------------------------
-   
+
     def build_script(self):
         if sys.platform in ("win32", "cygwin"):
             script_ext = ".bat"