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Merge pull request #2082 from enjoy-digital/efinix_iface_signal_names
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Efinix iface signal names.
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@enjoy-digital
enjoy-digital authored Sep 26, 2024
2 parents c3e8736 + 39d292a commit b11cc8c
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Showing 2 changed files with 43 additions and 8 deletions.
27 changes: 19 additions & 8 deletions litex/build/efinix/common.py
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,11 @@
r"\g<0>" + colorama.Style.RESET_ALL),
]

# Helpers ------------------------------------------------------------------------------------------

def assert_is_signal_or_clocksignal(obj):
assert isinstance(obj, (ClockSignal, Signal)), f"Object {obj} is not a ClockSignal or Signal"

# Efinix AsyncResetSynchronizer --------------------------------------------------------------------

class EfinixAsyncResetSynchronizerImpl(Module):
Expand Down Expand Up @@ -104,12 +109,13 @@ def lower(dr):

class EfinixClkOutputImpl(Module):
def __init__(self, platform, i, o):
assert_is_signal_or_clocksignal(i)
block = {
"type" : "GPIO",
"size" : 1,
"location" : platform.get_pin_location(o)[0],
"properties" : platform.get_pin_properties(o),
"name" : i.name_override, # FIXME
"name" : i,
"mode" : "OUTPUT_CLK",
}
platform.toolchain.ifacewriter.blocks.append(block)
Expand Down Expand Up @@ -268,6 +274,7 @@ def lower(dr):
class EfinixDDRTristateImpl(Module):
def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk):
assert oe1 == oe2
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(io)
io_pad = platform.get_pin_location(io)
io_prop = platform.get_pin_properties(io)
Expand All @@ -290,9 +297,9 @@ def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk):
"properties" : io_prop,
"size" : 1,
"in_reg" : "DDIO_RESYNC",
"in_clk_pin" : clk.name_override, # FIXME.
"in_clk_pin" : clk,
"out_reg" : "DDIO_RESYNC",
"out_clk_pin" : clk.name_override, # FIXME.
"out_clk_pin" : clk,
"oe_reg" : "REG",
"is_inclk_inverted" : False,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
Expand All @@ -309,6 +316,7 @@ def lower(dr):

class EfinixSDRTristateImpl(EfinixDDRTristateImpl):
def __init__(self, platform, io, o, oe, i, clk):
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(io)
io_pad = platform.get_pin_location(io)
io_prop = platform.get_pin_properties(io)
Expand All @@ -327,9 +335,9 @@ def __init__(self, platform, io, o, oe, i, clk):
"properties" : io_prop,
"size" : 1,
"in_reg" : "REG",
"in_clk_pin" : clk.name_override, # FIXME.
"in_clk_pin" : clk,
"out_reg" : "REG",
"out_clk_pin" : clk.name_override, # FIXME.
"out_clk_pin" : clk,
"oe_reg" : "REG",
"is_inclk_inverted" : False,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
Expand All @@ -347,6 +355,7 @@ def lower(dr):

class EfinixSDROutputImpl(Module):
def __init__(self, platform, i, o, clk):
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(o)
io_pad = platform.get_pin_location(o)
io_prop = platform.get_pin_properties(o)
Expand All @@ -361,7 +370,7 @@ def __init__(self, platform, i, o, clk):
"properties" : io_prop,
"size" : 1,
"out_reg" : "REG",
"out_clk_pin" : clk.name_override, # FIXME.
"out_clk_pin" : clk,
"is_inclk_inverted" : False,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
}
Expand All @@ -379,6 +388,7 @@ def lower(dr):

class EfinixDDROutputImpl(Module):
def __init__(self, platform, i1, i2, o, clk):
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(o)
io_pad = platform.get_pin_location(o)
io_prop = platform.get_pin_properties(o)
Expand All @@ -395,7 +405,7 @@ def __init__(self, platform, i1, i2, o, clk):
"properties" : io_prop,
"size" : 1,
"out_reg" : "DDIO_RESYNC",
"out_clk_pin" : clk.name_override, # FIXME.
"out_clk_pin" : clk,
"is_inclk_inverted" : False,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
}
Expand All @@ -411,6 +421,7 @@ def lower(dr):

class EfinixDDRInputImpl(Module):
def __init__(self, platform, i, o1, o2, clk):
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(i)
io_pad = platform.get_pin_location(i)
io_prop = platform.get_pin_properties(i)
Expand All @@ -426,7 +437,7 @@ def __init__(self, platform, i, o1, o2, clk):
"properties" : io_prop,
"size" : 1,
"in_reg" : "DDIO_RESYNC",
"in_clk_pin" : clk.name_override, # FIXME.
"in_clk_pin" : clk,
"is_inclk_inverted" : False
}
platform.toolchain.ifacewriter.blocks.append(block)
Expand Down
24 changes: 24 additions & 0 deletions litex/build/efinix/efinity.py
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Original file line number Diff line number Diff line change
Expand Up @@ -222,9 +222,33 @@ def _build_iface_gpio(self):

return "\n".join(conf)

def resolve_iface_signal_names(self):
# Iterate over each block
for block in self.platform.toolchain.ifacewriter.blocks:

# Iterate over each key-value pair in the block
for key, value in block.items():

# Only process specific keys, skip others.
if key not in ["name", "in_clk_pin", "out_clk_pin"]:
continue

# If the value is a ClockSignal, resolve its name
if isinstance(value, ClockSignal):
clock_domain = value.cd
signal_name = self._vns.get_name(self._vns.clock_domains[clock_domain].clk)
block[key] = signal_name # Replace with the resolved name

# If the value is a Signal, directly resolve its name
elif isinstance(value, Signal):
signal_name = self._vns.get_name(value)
block[key] = signal_name # Replace with the resolved name

def build_io_constraints(self):
pythonpath = ""

self.resolve_iface_signal_names()

header = self.ifacewriter.header(self._build_name, self.platform.device)
gen = self.ifacewriter.generate(self.platform.device)
#TODO : move this to ifacewriter
Expand Down

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