build/sim/core/veril.cpp: Flush trace file on finish, fix issue with …

…empty .fst dumps with short simulations.
enjoy-digital · Sep 25, 2024 · b86d76b · b86d76b
1 parent c95a6e0
commit b86d76b
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diff --git a/CHANGES.md b/CHANGES.md
@@ -11,6 +11,7 @@
 	- soc/cores/clock/colognechip   : Fixed and reworked locked signal handling.
 	- litesdcard                    : Fixed data_i sampling (https://github.com/enjoy-digital/litesdcard/pull/34).
 	- litespi/mmap                  : Fixed dummy bits (https://github.com/litex-hub/litespi/pull/71).
+	- sim/verilator                 : Fixed .fst empty dump with short simulation.
 
 	[> Added
 	--------

diff --git a/litex/build/sim/core/veril.cpp b/litex/build/sim/core/veril.cpp
@@ -78,6 +78,7 @@ extern "C" void litex_sim_tracer_dump()
 
 extern "C" int litex_sim_got_finish()
 {
+  tfp->flush();
   return Verilated::gotFinish();
 }