cpu/vexiiriscv integration

[Dolu1990]

Do not merge yet (WIP)

Hi,
This PR add VexiiRiscv in Litex. Here is an example to generate a quad-core linux capable RISC-V on digilent_nexys_video :

(single issue, RV32IMASU, linux ready, performances look quite good so far)

Just a few info about VexiiRiscv config.
It came into 3 base cpu-variant (standard, linux, debian), but then on the top of that, there is quite a few parameters which can make a big inpact on performances.

For instance, when i'm testing it to run debian on max performance i do :

python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --cpu-variant=debian --with-jtag-tap  --bus-standard axi-lite \
--vexii-args="--lsu-software-prefetch --lsu-hardware-prefetch rpt --performance-counters 9 --regfile-async --lsu-l1-store-buffer-ops=32  --lsu-l1-store-buffer-slots=4 --lsu-l1-refill-count 4 --lsu-l1-writeback-count 4" \
--cpu-count=4 --with-jtag-tap  --with-video-framebuffer --l2-self-flush=40c00000,40dd4c00,1666666  --with-sdcard --with-ethernet --with-coherent-dma --l2-byte=262144  --sys-clk-freq 100000000 \
--update-repo=no --soc-json build/csr.json --build   --load

Here is an overview:

Arguements which goes into the --vexii-args="xxxx"

• --lsu-software-prefetch --lsu-hardware-prefetch rpt For fast sequencial memory accesses
• --lsu-l1-store-buffer-ops=32 --lsu-l1-store-buffer-slots=4 To avoid to stall the CPU on store miss
• --lsu-l1-refill-count 4 --lsu-l1-writeback-count 4 To allow the data cache to have multiple inflight memory requests
• --relaxed-btb to improve timings of the BTB at the cost of 1 cycle penality per predicted taken branch/jump

Soc level arguements

• --l2-byte=262144 Enable the Vexii shared L2 cache
• --l2-self-flush=40c00000,40dd4c00,1666666 is a workaround which will periodicaly flush a given memory space in the L2 to ensure the video DMA get updated pictures

[Dolu1990]

Here is an example of a debian ready dual core (WIP) :

python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv  --with-jtag-tap  --bus-standard axi-lite --vexii-args=" \
--allow-bypass-from=0 --debug-privileged --with-mul --with-div --div-ipc --with-rva --with-supervisor --performance-counters 0 \
--regfile-async --xlen=64 --with-rvc --with-rvf --with-rvd --fma-reduced-accuracy \
--fetch-l1 --fetch-l1-ways=4 --fetch-l1-mem-data-width-min=64 \
--lsu-l1 --lsu-l1-ways=4  --lsu-l1-mem-data-width-min=64 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --lsu-l1-store-buffer-slots=2  --with-lsu-bypass \
--with-btb --with-ras --with-gshare --relaxed-branch"  --cpu-count=2 --with-jtag-tap  --with-video-framebuffer --with-sdcard --with-ethernet --with-coherent-dma --l2-byte=131072 --update-repo=no  --sys-clk-freq 100000000 --build   --load

[Dolu1990]

Updated it with 3 base variant :
cached, linux, debian

On digilent video :

# debian ready : 
python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --cpu-variant=debian  --cpu-count=1 --with-video-framebuffer --with-sdcard --with-ethernet --with-coherent-dma --build --load

#debian ready with more perf 
python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --cpu-variant=debian --bus-standard axi-lite --vexii-args="--regfile-async --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --lsu-l1-store-buffer-slots=2" --cpu-count=4 --with-jtag-tap  --with-video-framebuffer --with-sdcard --with-ethernet --with-coherent-dma --l2-byte=262144  --build --load

[Dolu1990]

@enjoy-digital
Hi,
I think this is ok for merge now :)

[enjoy-digital]

Awesome, thanks @Dolu1990!

[Dolu1990]

Documentation about how to deploy buildroot / debian here :

• https://github.com/SpinalHDL/VexiiRiscv/tree/dev/doc/litex/debian
• https://github.com/SpinalHDL/VexiiRiscv/tree/dev/doc/litex/buildroot

[enjoy-digital]

Great, thanks @Dolu1990!