soc/cores/hyperbus: Full rewrite of HyperRAM core. #2053
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Rewriting the HyperRAM core to improve its design and functionality. The old core grew complex over time without a clear structure. This new version offers: - IO registers on all signals for better performance. - Flexible clocking options. - Simplified architecture. - Easier to extend with new features. This rewrite provides a base for future development.
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Rewriting the HyperRAM core to improve its design and functionality. The old core grew complex over time without a clear structure. This new version offers:
This rewrite provides a base for future development.