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build/efinix: add a few IO primitives, IO constraints, sdc rework #2060

Merged
merged 5 commits into from
Sep 10, 2024
Merged

build/efinix: add a few IO primitives, IO constraints, sdc rework #2060

merged 5 commits into from
Sep 10, 2024

Commits on Sep 5, 2024

  1. build/efinix: add a few IO primitives, IO constraints, but mainly it … 

    …rework how the SDC are handled
    @Dolu1990
    Dolu1990 committed Sep 5, 2024
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  2. litex/build/efinix/common.py add EfinixDDRTristate binding 

    Co-authored-by: Fin Maaß <[email protected]>
    @Dolu1990 @maass-hamburg
    Dolu1990 and maass-hamburg authored Sep 5, 2024
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Commits on Sep 10, 2024

  1. build/efinix/common.py: replaced i as str by a ClockDomain

    @trabucayre
    trabucayre committed Sep 10, 2024
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  2. soc/cores/clock/efinix.py: register_clkin: uses clkin.name_override a… 

    …s input_signal name when name is not provided and PLL is configured in CORE or INTERNAL mode, create_clkout: added PLL name in clk_name str
    @trabucayre
    trabucayre committed Sep 10, 2024
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  3. soc/cores/clock/efinix.py: fill platform.clks with clkout mapping cd/… 

    …clk_out_name. litex/build/efinix/ifacewriter.py: generate_lvds: when slow_clk/fast_clk are ClockSignal uses platform.clks to map between domain and signal name
    @trabucayre
    trabucayre committed Sep 10, 2024
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