Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

build: efinix: common.py; add SDRInput #2081

Merged

Conversation

maass-hamburg
Copy link
Contributor

add SDRInput for efinix

add `SDRInput` for efinix

Signed-off-by: Fin Maaß <[email protected]>
@enjoy-digital enjoy-digital merged commit 0e337e2 into enjoy-digital:master Sep 26, 2024
1 check passed
@enjoy-digital
Copy link
Owner

Thanks, this is merged.

@enjoy-digital
Copy link
Owner

@maass-hamburg: I had to disable it for now with b135f71 since breaking a design the RMII Ethernet PHY, we'll have a look.

@maass-hamburg
Copy link
Contributor Author

@enjoy-digital maybe it's a timing problem. Maybe try to driving the ref_clk via a ClkOutput directly from the PLL with a phase of 90° to the ethernet clock. That's what we are doing and it's working.

@enjoy-digital
Copy link
Owner

@maass-hamburg: It's a build issue with verilog/iface.py not correctly generated, but I haven't had the time to look at it more closely yet. Probably not related to the change itself.

@maass-hamburg maass-hamburg deleted the build_efinix_add_sdr_input branch October 1, 2024 06:03
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants