Update top.v

f4pga · Jul 9, 2023 · 93e64d6 · 93e64d6
1 parent e0094c7
commit 93e64d6
Showing 1 changed file with 15 additions and 15 deletions.
diff --git a/xilinx/xc7/tests/dsp/top.v b/xilinx/xc7/tests/dsp/top.v
@@ -1,5 +1,5 @@
 `timescale 1ns / 1ps
-
+// Structural instantiation of dsp48e1 block in 25x18 multiplier mode using pipelining registers(A1,A2,B1,B2). 
 module top
   (
    A, 
@@ -49,20 +49,20 @@ module top
    	.C(48'b111111111111111111111111111111111111111111111111),   
         .CARRYIN(1'b0),
         .CARRYINSEL(3'b000),
-        .CEA1(1'b0),
-        .CEA2(1'b0),
-        .CEAD(1'b0),
-        .CEALUMODE(1'b0),
-        .CEB1(1'b0),
-        .CEB2(1'b0),
-        .CEC(1'b0),
-        .CECARRYIN(1'b0),
-        .CECTRL(1'b0),
-        .CED(1'b0),
-        .CEINMODE(1'b0),
-        .CEM(1'b0),
-        .CEP(1'b0),
-        .CLK(1'b0),
+     .CEA1(1'b1),
+     .CEA2(1'b1),
+     .CEAD(1'b1),
+     .CEALUMODE(1'b1),
+     .CEB1(1'b1),
+     .CEB2(1'b1),
+     .CEC(1'b1),
+     .CECARRYIN(1'b1),
+     .CECTRL(1'b1),
+     .CED(1'b1),
+     .CEINMODE(1'b1),
+     .CEM(1'b1),
+     .CEP(1'b1),
+     .CLK(1'b1),
         .D(25'b0000000000000000000000000),
         .INMODE(5'b00000),        
         .OPMODE(7'b0111111),