This repo contains the codes which I implemented while completing the course "Building a RISC-V CPU Core" offered by Linux Foundation through edx. The processor has a support of base integer RV32I instruction format written in TL- Verilog on Makerchip platform.
RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established RISC principles.Unlike most other ISA designs, RISC-V is provided under open source licenses that do not require fees to use. RISC-V is also popular for it's simplicity and extensibility and infact RISC stands for Reduced Instruction Set Architecture.
It contains 32 registers and most instructions are read from or written to the register file. RISC-V is based on load-store architecture as load and store instructions tranfers between register file and the memory.
Some instructions :p
More details on 32 bit RISC-V ISA can be found here