2021-10-19 (v2.0.0)

- add support for the Arty A7 100T board
- update flash part for Arty A7 35T board
- remove many unnecessary files
- increase Java memory to speed up the build
- test with Debian 11.1 bullseye 5.10.70-1 (2021-09-30)
- test with Vivado 2021.1
- test with Hex Five riscv-gnu-toolchain-20210618
- test with MultiZone Security TEE v2.2.1
- test with MultiZone Trusted Firmware v2.2.1
- update release assets with new bitstreams
- update readme

Makefile.x300arty100devkit

@@ -0,0 +1,23 @@
+# See LICENSE for license details.
+# Modifications copyright (C) 2019 Hex-Five
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+BUILD_DIR := $(base_dir)/builds/x300arty100devkit
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
+MODEL := X300ArtyDevKitFPGAChip
+PROJECT := hexfive.x300artydevkit
+export CONFIG_PROJECT := hexfive.x300artydevkit
+export CONFIG := X300ArtyDevKitConfig
+export BOARD := arty_a7_100
+export BOOTROM_DIR := $(base_dir)/bootrom/xip
+
+rocketchip_dir := $(base_dir)/rocket-chip
+sifiveblocks_dir := $(base_dir)/sifive-blocks
+VSRCS := \
+	$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
+	$(sifiveblocks_dir)/vsrc/SRLatch.v \
+	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
+
+include common.mk

Makefile.x300artydevkit → Makefile.x300arty35devkit

@@ -1,7 +1,7 @@
 # See LICENSE for license details.
 # Modifications copyright (C) 2019 Hex-Five
 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
-BUILD_DIR := $(base_dir)/builds/x300artydevkit
+BUILD_DIR := $(base_dir)/builds/x300arty35devkit
 FPGA_DIR := $(base_dir)/fpga-shells/xilinx
 MODEL := X300ArtyDevKitFPGAChip
 PROJECT := hexfive.x300artydevkit

README.md

@@ -1,74 +1,93 @@
 # X300
 
-This repository contains the X300, a secure version of [SiFive's Freedom E300
-Platform](https://github.com/sifive/freedom/tree/3624efff1819e52cec30c72f9085158189f8b53f)
-modified to work with the free and open [MultiZone Secure IoT Stack](https://github.com/hex-five/multizone-secure-iot-stack).
+This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 SoC is Hex Five's official reference platform for its [MultiZone Security Trusted Execution Environment](https://github.com/hex-five/multizone-sdk) and [MultiZone Security Trusted Firmware](https://github.com/hex-five/multizone-iot-sdk). The X300 is an enhanced secure version of the - now archived - [SiFive's Freedom E300 Platform](https://github.com/sifive/freedom) built around the RISC-V Rocket chip originally developed at U.C. Berkeley.
 
 Feature comparison between E300 (not secure) and X300 (secure):
 
 | E300             | X300                                         |
 | ---------------- | -------------------------------------------- |
-| RV32ACIM         | RV32ACIMU                                    |
+| RV32IMAC         | RV32IMACU - 'U' mode support for TEE         |
+| no PMP           | 8 Physical Memory Protection registers       |
 | 32.5 MHz clock   | 65 MHz clock                                 |
 | 2 HW breakpoints | 8 HW breakpoints                             |
-| no Ethernet core | Xilinx EthernetLite Ethernet core            |
+| no Ethernet core | Xilinx EthernetLite Ethernet 10/100 core     |
 | 1-way icache     | 4-way icache                                 |
-| no ITIM          | ITIM at 0x0800\_0000                         |
-| 16 kB DTIM       | 64 kB DTIM                                   |
-| no perf counters | 2 perf counters, hpmcounter3 and hpmcounter4 |
-| no CLICs         | 3 CLICs (BTN0, BTN1 and BTN2)                |
+| no ITIM          | 16KB ITIM at 0x08000000                      |
+| 16 KB DTIM       | 64KB DTIM at 0x80000000                      |
+| no perf counters | 2 perf counters: hpmcounter3 and hpmcounter4 |
+| no BTN mappings  | 3 CLINT sources: BTN0, BTN1, and BTN2        |
 
-Like the Freedom E300 Arty FPGA Dev Kit, the X300 is designed to be mapped onto
-an [Arty FPGA Evaluation
-Kit](https://www.xilinx.com/products/boards-and-kits/arty.html).
+Like the Freedom E300 Arty FPGA Dev Kit, the X300 is designed to work with the [Digilent Arty A7 FPGA Evaluation Kit](https://digilent.com/reference/programmable-logic/arty-a7/start) in the 35T or 100T version.
 
 ### Bootrom
 
-The default bootrom consists of a program that immediately jumps to address
-0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty
-board.
+The default bootrom consists of a program that immediately jumps to address 0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty board. The provided bitstream files includes no firmware. A fully functional state-of-the-art secure firmware stack for this device is available at https://github.com/hex-five/multizone-iot-sdk. 
+
+### Quick Start
+
+Prebuilt bitstream files are provided as release assets ready to download and program.
+
+- [X300ArtyA7-35T.mcs](https://github.com/hex-five/multizone-fpga/releases/download/v2.0.0/X300ArtyA7-35T.mcs)
+- [X300ArtyA7-100T.mcs](https://github.com/hex-five/multizone-fpga/releases/download/v2.0.0/X300ArtyA7-100T.mcs)
+
+If you don't need to modify the hardware design, you can skip the next sections and jump directly to the `Program` section.
 
 ## Requirements
 
-### Vivado 2017.1 (or later)
+### Xilinx Vivado Design Suite
 
-You'll need Vivado to synthesize the bistream for the Arty FPGA. You should
-have received a Xilinx single node license and instructions how to install Vivado with
-your Arty FPGA Dev Kit.
+You need the [Xilinx Vivado Design Suite](https://www.xilinx.com/support/download.html) to synthesize and/or upload the bistream for the Arty FPGA. You should have received a Xilinx single node license and instructions how to install Vivado with your Arty FPGA Dev Kit. If you are not interested in hardware development and just need to flash the X300 bitstream to run RISC-V firmware, you may prefer the Vivado Lab edition, which is smaller, quicker to download and install, and doesn't require license.
 
 ### RISC-V Toolchain
 
-To compile the bootloader for the X300, the RISC-V software toolchain must be
-installed locally and the $(RISCV) environment variable must point to the
-location of where the RISC-V toolchains are installed. We recommend you build
-the toolchain yourself from
-[riscv/riscv-gnu-toolchain](https://github.com/riscv/riscv-gnu-toolchain/tree/411d1345507e5313c3575720f128be9e6c0ed941)
+To compile the bootloader for the X300, the RISC-V software toolchain must be installed locally and the `RISCV` environment variable must point to the location of the install. We recommend Hex Five's reference build freely available for download at https://hex-five.com/wp-content/uploads/riscv-openocd-20210618.tar.xz or you can use the one included in the rocket-chip submodule.
+
+```
+wget https://hex-five.com/wp-content/uploads/riscv-gnu-toolchain-20210618.tar.xz
+tar -xvf riscv-gnu-toolchain-20210618.tar.xz
+```
+
+## Build
 
-Run the following commands to clone the repository and get started:
+Run the following commands to clone repository and submodules:
 
-```sh
+```
 $ git clone https://github.com/hex-five/multizone-fpga.git
 $ cd multizone-fpga
-$ git submodule update --init --recursive
+$ git submodule update --init --recursive --jobs 8
+```
+
+In order to make the `mcs` target, you need the Vivado executable on your `PATH` and the `RISCV` environment variable pointing to your local toolchain. Change these values according to your setup:
 ```
+export PATH=$PATH:~/Xilinx/Vivado/2021.1/bin
+export RISCV=~/riscv-gnu-toolchain-20210618
 
-## Building
+```
 
-To compile the bistream, run
+To build the bitstream, run one of these two scripts according to your target:
 
-```sh
-$ make -f Makefile.x300artydevkit mcs
 ```
+$ make -f Makefile.x300arty35devkit mcs
+```
+or
+```
+$ make -f Makefile.x300arty100devkit mcs
+```
+
+*Note: if the first build ends prematurely after resolving Scala dependencies, just reenter the command a second time.*
 
-These will place the files under `builds/x300artydevkit/obj`.
 
-Note that in order to run the `mcs` target, you need to have the `vivado`
-executable on your `PATH`.
+These will place the bitstream file `X300ArtyDevKitFPGAChip.mcs` under `builds/x300artyXXXdevkit/obj`.
 
-## Running
+## Program
 
-For instructions for getting the generated image onto an FPGA and programming
-it with software using the [Freedom E
-SDK](https://github.com/sifive/freedom-e-sdk), please see the [Freedom E310
-Arty FPGA Dev Kit Getting Started
-Guide](https://www.sifive.com/documentation/freedom-soc/freedom-e300-arty-fpga-dev-kit-getting-started-guide/).
+To program the SPI flash with Vivado:
+- Launch Vivado
+- Open Hardware Manager, click the auto-connect icon, and open the target board
+- Right click on the FPGA device and select ”Add Configuration Memory Device”
+- Select Part "s25fl128sxxxxxx0-spi-x1_x2_x4" ("mt25ql128-spi-x1_x2_x4" if you have an old Arty 35T)
+- Click OK to ”Do you want to program the configuration memory device now?”
+- Add X300ArtyA7-35T.mcs or X300ArtyA7-100T.mcs depending on your board
+- Select OK
+- Once the programming completes in Vivado, press the “PROG” Button on the Arty board to
+load the image into the FPGA

common.mk

@@ -32,7 +32,7 @@ SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.4
 
 # Build firrtl.jar and put it where chisel3 can find it.
 FIRRTL_JAR ?= $(rocketchip_dir)/firrtl/utils/bin/firrtl.jar
-FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
+FIRRTL ?= java -Xmx4G -Xss16M -cp $(FIRRTL_JAR) firrtl.Driver
 
 $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.scala")
 	$(MAKE) -C $(rocketchip_dir)/firrtl SBT="$(SBT)" root_dir=$(rocketchip_dir)/firrtl build-scala