Merge pull request #229 from harshkhandeparkar/ldo-simulation

[GSoC] Updated LDO Simulations
idea-fasoc · Oct 9, 2023 · f0dcc71 · f0dcc71
2 parents 708f2ac + 97aa886
commit f0dcc71
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Showing 11 changed files with 118 additions and 466 deletions.
diff --git a/openfasoc/generators/ldo-gen/.gitignore b/openfasoc/generators/ldo-gen/.gitignore
@@ -0,0 +1 @@
+work/
diff --git a/openfasoc/generators/ldo-gen/flow/.gitignore b/openfasoc/generators/ldo-gen/flow/.gitignore
@@ -0,0 +1,8 @@
+design/sky130hvl/ldo/config.mk
+logs/
+objects/
+reports/
+results/
+/*.log
+/*.spice
+/*.ext
diff --git a/openfasoc/generators/ldo-gen/simulations/.gitignore b/openfasoc/generators/ldo-gen/simulations/.gitignore
@@ -0,0 +1 @@
+run/
diff --git a/openfasoc/generators/ldo-gen/simulations/templates/ldo_load_change_ngspice.sp b/openfasoc/generators/ldo-gen/simulations/templates/ldo_load_change_ngspice.sp
@@ -1,19 +1,19 @@
 * VREG and load current Transient
 
 * include from .../sky130A/libs.tech/ngspice/sky130.lib.spice
-.lib '@model_file' @model_corner
+.lib '${model_file}' ${model_corner}
 * include the LDO spice netlist
-.include 'ldo_sim.spice'
+.include '${netlist_path}'
 
 
-xi1 @proper_pin_ordering
+xi1 ${pin_ordering}
 + ldoInst
 
 *Controls
 V0 VSS 0 DC=0
 V1 VDD 0 DC=3.3
 * to be commented if using Analog Vref block
-V2 VREF 0 DC=@VALUE_REF_VOLTAGE
+V2 VREF 0 DC=${vref}
 
 vtrim1 trim1 0 DC=0
 vtrim2 trim2 0 DC=0
@@ -46,7 +46,7 @@ vstd7 std_pt_in_cnt[7] 0 dc 0
 vstd8 std_pt_in_cnt[8] 0 dc 0
 
 *Load change
-V10 VR 0 pwl 0 1800 20u 1800 20.01u @Res_Value
+V10 VR 0 pwl 0 1800 20u 1800 20.01u ${1.2 * vref / max_load}
 R1 VREG 0 R=V(VR)
 C1 VREG VSS 5p
 
@@ -57,13 +57,14 @@ C1 VREG VSS 5p
 
 *Analysis
 .temp 25
-.tran @sim_step @sim_time
+<% sim_end_time = 1.2 * arr_size / 1000000 %>
+.tran ${sim_end_time / 2000} ${sim_end_time}
 
 .control
 run
 
 set filetype=binary
-write @output_raw v(VREG) v(VREF) v(cmp_out) v(clk) v("ctrl_out[0]") v("ctrl_out[1]") v("ctrl_out[2]") v("ctrl_out[3]") v("ctrl_out[4]") v("ctrl_out[5]") v("ctrl_out[6]") v("ctrl_out[7]") v("ctrl_out[8]") i(V1)
+write ${f"{max_load * 1000}mA_output_load_change.raw"} v(VREG) v(VREF) v(cmp_out) v(clk) v("ctrl_out[0]") v("ctrl_out[1]") v("ctrl_out[2]") v("ctrl_out[3]") v("ctrl_out[4]") v("ctrl_out[5]") v("ctrl_out[6]") v("ctrl_out[7]") v("ctrl_out[8]") i(V1)
 
 .endc
 

diff --git a/openfasoc/generators/ldo-gen/simulations/templates/ldo_load_change_xyce.sp b/openfasoc/generators/ldo-gen/simulations/templates/ldo_load_change_xyce.sp
@@ -1,19 +1,19 @@
 * VREG and load current Transient
 
 * include from .../sky130A/libs.tech/ngspice/sky130.lib.spice
-.lib '@model_file' @model_corner
+.lib '${model_file}' ${model_corner}
 * include the LDO spice netlist
-.include 'ldo_sim.spice'
+.include '${netlist_path}'
 
 
-xi1 @proper_pin_ordering
+xi1 ${pin_ordering}
 + ldoInst
 
 *Controls
 V0 VSS 0 dc 0
 V1 VDD 0 dc 3.3
 * to be commented if using Analog Vref block
-V2 VREF 0 dc @VALUE_REF_VOLTAGE
+V2 VREF 0 dc ${vref}
 
 vtrim1 trim1 0 dc 0
 vtrim2 trim2 0 dc 0
@@ -46,7 +46,7 @@ vstd7 std_pt_in_cnt[7] 0 dc 0
 vstd8 std_pt_in_cnt[8] 0 dc 0
 
 *Load change
-V10 VR 0 pwl 0 1800 20u 1800 20.01u @Res_Value
+V10 VR 0 pwl 0 1800 20u 1800 20.01u ${1.2 * vref / max_load}
 R1 VREG 0 R=V(VR)
 C1 VREG VSS 5p
 
@@ -55,7 +55,8 @@ C1 VREG VSS 5p
 .PREPROCESS ADDRESISTORS ONETERMINAL 1G
 *Analysis
 
-.tran @sim_step @sim_time UIC
+<% sim_end_time = 1.2 * arr_size / 1000000 %>
+.tran ${sim_end_time / 2000} ${sim_end_time} UIC
 
-.print tran format=raw file=@output_raw v(VREG) v(VREF) v(cmp_out) v(ctrl_out[0]) v(ctrl_out[1]) v(ctrl_out[2]) v(ctrl_out[3]) v(ctrl_out[4]) v(ctrl_out[5]) v(ctrl_out[6]) v(ctrl_out[7]) v(ctrl_out[8]) i(V1)
+.print tran format=raw file=${f"{max_load * 1000}mA_output_load_change.raw"} v(VREG) v(VREF) v(cmp_out) v(ctrl_out[0]) v(ctrl_out[1]) v(ctrl_out[2]) v(ctrl_out[3]) v(ctrl_out[4]) v(ctrl_out[5]) v(ctrl_out[6]) v(ctrl_out[7]) v(ctrl_out[8]) i(V1)
 .end
diff --git a/openfasoc/generators/ldo-gen/simulations/templates/ldo_tran_ngspice.sp b/openfasoc/generators/ldo-gen/simulations/templates/ldo_tran_ngspice.sp
@@ -1,19 +1,19 @@
 * VREG and load current Transient
 
 * include from .../sky130A/libs.tech/ngspice/sky130.lib.spice
-.lib '@model_file' @model_corner
+.lib '${model_file}' ${model_corner}
 * include the LDO spice netlist
-.include 'ldo_sim.spice'
+.include '${netlist_path}'
 
 
-xi1 @proper_pin_ordering
+xi1 ${pin_ordering}
 + ldoInst
 
 *Controls
 V0 VSS 0 DC=0
 V1 VDD 0 DC=3.3
 * to be commented if using Analog Vref block
-V2 VREF 0 DC=@VALUE_REF_VOLTAGE
+V2 VREF 0 DC=${vref}
 
 vtrim1 trim1 0 DC=0
 vtrim2 trim2 0 DC=0
@@ -28,7 +28,7 @@ vtrim10 trim10 0 DC=0
 
 *With ideal VRef block
 *change here if want to change clock frequency
-V3 clk VSS pulse 0 3.3 0 1n 1n @duty_cycle @clk_period
+V3 clk VSS pulse 0 3.3 0 1n 1n ${0.5 / freq} ${1 / freq}
 
 V4 reset 0 pwl 0 3.3 10n 3.3 10.1n 0
 
@@ -45,24 +45,25 @@ vstd6 std_pt_in_cnt[6] 0 dc 0
 vstd7 std_pt_in_cnt[7] 0 dc 0
 vstd8 std_pt_in_cnt[8] 0 dc 0
 
-R1 VREG VSS @Res_Value
+R1 VREG VSS ${1.2 * vref / max_load}
 *Resistance 3600 --> 0.5 mA for 1.8 V reference voltage. R to be adjusted according to Iload and output voltage.
 
-C1 VREG VSS @Cap_Value
+C1 VREG VSS ${cap}
 
 *.options savecurrents
 .option wnflag=1
 .options rshunt=1e11
 .ic v(VREG) = 0 v(clk)=0 v(reset)=3.3
 *Analysis
 .temp 25
-.tran @sim_step @sim_time
+<% sim_end_time = 1.2 * arr_size / freq %>
+.tran ${sim_end_time / 2000} ${sim_end_time}
 
 .control
 run
 
 set filetype=binary
-write @output_raw v(VREG) v(VREF) v(cmp_out) v(clk) v("ctrl_out[0]") v("ctrl_out[1]") v("ctrl_out[2]") v("ctrl_out[3]") v("ctrl_out[4]") v("ctrl_out[5]") v("ctrl_out[6]") v("ctrl_out[7]") v("ctrl_out[8]")
+write ${f"{max_load * 1000}mA_{freq}Hz_{cap}_cap_output.raw"} v(VREG) v(VREF) v(cmp_out) v(clk) v("ctrl_out[0]") v("ctrl_out[1]") v("ctrl_out[2]") v("ctrl_out[3]") v("ctrl_out[4]") v("ctrl_out[5]") v("ctrl_out[6]") v("ctrl_out[7]") v("ctrl_out[8]")
 
 .endc
 

diff --git a/openfasoc/generators/ldo-gen/simulations/templates/ldo_tran_xyce.sp b/openfasoc/generators/ldo-gen/simulations/templates/ldo_tran_xyce.sp
@@ -1,19 +1,19 @@
 * VREG and load current Transient
 
 * include from .../sky130A/libs.tech/ngspice/sky130.lib.spice
-.lib '@model_file' @model_corner
+.lib '${model_file}' ${model_corner}
 * include the LDO spice netlist
-.include 'ldo_sim.spice'
+.include '${netlist_path}'
 
 
-xi1 @proper_pin_ordering
+xi1 ${pin_ordering}
 + ldoInst
 
 *Controls
 V0 VSS 0 dc 0
 V1 VDD 0 dc 3.3
 * to be commented if using Analog Vref block
-V2 VREF 0 dc @VALUE_REF_VOLTAGE
+V2 VREF 0 dc ${vref}
 
 vtrim1 trim1 0 dc 0
 vtrim2 trim2 0 dc 0
@@ -28,7 +28,7 @@ vtrim10 trim10 0 dc 0
 
 *With ideal VRef block
 *change here if want to change clock frequency
-V3 clk VSS pulse 0 3.3 0 1n 1n @duty_cycle @clk_period
+V3 clk VSS pulse 0 3.3 0 1n 1n ${0.5 / freq} ${1 / freq}
 
 V4 reset 0 pwl 0 3.3 10n 3.3 10.1n 0
 
@@ -45,17 +45,18 @@ vstd6 std_pt_in_cnt[6] 0 dc 0
 vstd7 std_pt_in_cnt[7] 0 dc 0
 vstd8 std_pt_in_cnt[8] 0 dc 0
 
-R1 VREG VSS @Res_Value
+R1 VREG VSS ${1.2 * vref / max_load}
 *Resistance 3600 --> 0.5 mA for 1.8 V reference voltage. R to be adjusted according to Iload and output voltage.
 
-C1 VREG VSS @Cap_Value
+C1 VREG VSS ${cap}
 
 .ic v(VREG) = 0 v(clk)=0 v(reset)=3.3
 .options LINSOL type=klu
 .PREPROCESS ADDRESISTORS ONETERMINAL 1G
 *Analysis
 
-.tran @sim_step @sim_time UIC
+<% sim_end_time = 1.2 * arr_size / freq %>
+.tran ${sim_end_time / 2000} ${sim_end_time} UIC
 
-.print tran format=raw file=@output_raw v(VREG) v(VREF) v(cmp_out) v(ctrl_out[0]) v(ctrl_out[1]) v(ctrl_out[2]) v(ctrl_out[3]) v(ctrl_out[4]) v(ctrl_out[5]) v(ctrl_out[6]) v(ctrl_out[7]) v(ctrl_out[8]) i(V1)
+.print tran format=raw file=${f"{max_load * 1000}mA_{freq}Hz_{cap}_cap_output.raw"} v(VREG) v(VREF) v(cmp_out) v(ctrl_out[0]) v(ctrl_out[1]) v(ctrl_out[2]) v(ctrl_out[3]) v(ctrl_out[4]) v(ctrl_out[5]) v(ctrl_out[6]) v(ctrl_out[7]) v(ctrl_out[8]) i(V1)
 .end
diff --git a/openfasoc/generators/ldo-gen/simulations/templates/pwrarr_sweep_ngspice.sp b/openfasoc/generators/ldo-gen/simulations/templates/pwrarr_sweep_ngspice.sp
@@ -1,7 +1,7 @@
 * include from .../sky130A/libs.tech/ngspice/sky130.lib.spice
-.lib '@model_file' @model_corner
+.lib '${model_file}' ${model_corner}
 * include the LDO spice netlist
-.include 'power_array.spice'
+.include '${netlist_path}'
 
 
 xi1 VREG VDD VSS ldoInst
@@ -11,7 +11,7 @@ xi1 VREG VDD VSS ldoInst
 V0 VSS 0 dc 0
 *V1 VDD VSS pwl 0 0 2n 0 2.0001n 3.3
 V1 VDD VSS 3.3
-V2 VREF VSS @VALUE_REF_VOLTAGE
+V2 VREF VSS ${vref}
 R1 VREG VSS 1000
 C1 VREG VSS 1n
 

diff --git a/openfasoc/generators/ldo-gen/simulations/templates/pwrarr_sweep_xyce.sp b/openfasoc/generators/ldo-gen/simulations/templates/pwrarr_sweep_xyce.sp
@@ -1,7 +1,7 @@
 * include from .../sky130A/libs.tech/ngspice/sky130.lib.spice
-.lib '@model_file' @model_corner
+.lib '${model_file}' ${model_corner}
 * include the LDO spice netlist
-.include 'power_array.spice'
+.include '${netlist_path}'
 
 
 xi1 VREG VDD VSS ldoInst
@@ -11,7 +11,7 @@ xi1 VREG VDD VSS ldoInst
 V0 VSS 0 dc 0
 *V1 VDD VSS pwl 0 0 2n 0 2.0001n 3.3
 V1 VDD VSS dc 3.3
-V2 VREF VSS @VALUE_REF_VOLTAGE
+V2 VREF VSS ${vref}
 R1 VREG VSS 1000
 C1 VREG VSS 1n