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cascode common source block #339
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…ove the M2 north of M1.
…horizontal or vertical placement.
@chetanyagoyal / @srpathen , `Circuit 1 contains 6 devices, Circuit 2 contains 2 devices. *** MISMATCH *** Final result: Logging to file "/tmp/tmp4n_a1thr/cascode_common_source_lvs_lvs.rpt" disabled Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes. Subcircuit pins:
Cell pin lists are equivalent. Class cascode_common_source_lvs (0): Merged 8 parallel devices.
NET mismatches: Class fragments follow (with fanout counts): Net: w_n780_n522# |Net: IOUT
|
Circuit 1: cascode_common_source_lvs | Circuit 2: cascode_common_source_lvs |
---|---|
(no matching pin) | VIN |
(no matching pin) | VBIAS |
(no matching pin) | VSS |
(no matching pin) | IOUT |
proxyIOUT | (no matching pin) |
Cell pin lists for cascode_common_source_lvs and cascode_common_source_lvs altered to match.
Device classes cascode_common_source_lvs and cascode_common_source_lvs are equivalent.
Final result: Top level cell failed pin matching.
`
@chetanyagoyal could you kindly clarify the netlist function used for the LVS check as the lvs fail implies that the Netlist is not getting extracted with the correct pins. ` return Netlist( ` Also the extract scipt gave the following error whenused with the gds ` Magic 8.3 revision 464 - Compiled on Sat Mar 9 23:18:29 UTC 2024. |
Apologies for the late replies, you can just dump the netlist from the python function to a file ( Try modifying the function until the dumped netlist matches your expectations |
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Please address the comments and look through the code in the repo to debug, let us know if youre stuck after this
PR for a cascode common source . LVS is failing with
Final result: Top level cell failed pin matching
. Please review and let us know the function parameters for LVS.