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build(deps): bump hw/deps/litedram from f23cb80 to 4326fe7 #322

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build(deps): bump hw/deps/litedram from f23cb80 to 4326fe7 #322

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2 changes: 1 addition & 1 deletion hw/deps/litedram
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Submodule litedram updated 91 files
+48 −0 .github/workflows/ci.yml
+0 −82 .travis.yml
+3 −14 README.md
+163 −0 bench/arty.py
+333 −0 bench/common.py
+149 −0 bench/ddr3_mr_gen.py
+174 −0 bench/ddr4_mr_gen.py
+154 −0 bench/genesys2.py
+156 −0 bench/kc705.py
+174 −0 bench/kcu105.py
+165 −0 bench/xcu1525.py
+6 −4 examples/arty.yml
+7 −5 examples/genesys2.yml
+51 −0 examples/kcu105.yml
+6 −4 examples/nexys4ddr.yml
+42 −0 examples/ulx3s.yml
+8 −4 examples/versa_ecp5.yml
+51 −0 examples/xcu1525.yml
+96 −51 litedram/common.py
+8 −2 litedram/core/__init__.py
+7 −4 litedram/core/bandwidth.py
+6 −3 litedram/core/bankmachine.py
+11 −4 litedram/core/controller.py
+8 −5 litedram/core/crossbar.py
+34 −22 litedram/core/multiplexer.py
+7 −4 litedram/core/refresher.py
+19 −8 litedram/dfii.py
+0 −324 litedram/frontend/adaptation.py
+373 −0 litedram/frontend/adapter.py
+5 −2 litedram/frontend/axi.py
+8 −5 litedram/frontend/bist.py
+72 −50 litedram/frontend/dma.py
+72 −28 litedram/frontend/ecc.py
+34 −23 litedram/frontend/fifo.py
+49 −52 litedram/frontend/wishbone.py
+264 −77 litedram/gen.py
+296 −73 litedram/init.py
+277 −92 litedram/modules.py
+1 −1 litedram/phy/__init__.py
+5 −1 litedram/phy/dfi.py
+210 −231 litedram/phy/ecp5ddrphy.py
+103 −20 litedram/phy/gensdrphy.py
+135 −0 litedram/phy/lpddr4/README.md
+8 −0 litedram/phy/lpddr4/__init__.py
+410 −0 litedram/phy/lpddr4/basephy.py
+220 −0 litedram/phy/lpddr4/commands.py
+410 −0 litedram/phy/lpddr4/s7phy.py
+649 −0 litedram/phy/lpddr4/sim.py
+140 −0 litedram/phy/lpddr4/simphy.py
+387 −0 litedram/phy/lpddr4/simsoc.py
+89 −8 litedram/phy/model.py
+6 −7 litedram/phy/s6ddrphy.py
+227 −359 litedram/phy/s7ddrphy.py
+273 −322 litedram/phy/usddrphy.py
+445 −0 litedram/phy/utils.py
+5 −2 test/benchmark.py
+72 −25 test/common.py
+6 −0 test/gen_access_pattern.py
+6 −0 test/gen_config.py
+270 −0 test/phy_common.py
+70 −0 test/primitives/glbl.v
+113 −0 test/primitives/test_oserdese2.py
+112 −0 test/primitives/test_oserdese3.py
+40 −31 test/reference/ddr3_init.h
+42 −35 test/reference/ddr4_init.h
+2 −2 test/reference/ddr4_init.py
+24 −19 test/reference/sdr_init.h
+5 −2 test/run_benchmarks.py
+103 −0 test/spd_data/MTA4ATF51264HZ-2G3B1.csv
+103 −0 test/spd_data/MTA4ATF51264HZ-3G2E1.csv
+261 −136 test/test_adaptation.py
+408 −0 test/test_adapter.py
+5 −2 test/test_axi.py
+5 −2 test/test_bandwidth.py
+5 −2 test/test_bankmachine.py
+7 −4 test/test_bist.py
+5 −2 test/test_command_chooser.py
+39 −33 test/test_crossbar.py
+5 −2 test/test_dma.py
+8 −3 test/test_ecc.py
+9 −2 test/test_examples.py
+112 −118 test/test_fifo.py
+30 −19 test/test_init.py
+711 −0 test/test_lpddr4.py
+55 −3 test/test_modules.py
+5 −2 test/test_multiplexer.py
+249 −0 test/test_phy_utils.py
+5 −2 test/test_refresh.py
+5 −2 test/test_steerer.py
+5 −2 test/test_timing.py
+21 −10 test/test_wishbone.py